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PRELIMINARY
INTEL® StrataFlash™ MEMORY TECHNOLOGY
32 AND 64 MBIT
28F320J5 and 28F640J5
High-Density Symmetrically-Blocked
Architecture
64 128-Kbyte Erase Blocks (64 M)
32 128-Kbyte Erase Blocks (32 M)
4.5 V–5.5 V V
CC
Operation
2.7 V–3.6 V and 4.5 V–5.5 V I/O
Capable
Configurable x8 or x16 I/O
100 ns Read Access Time (32 M)
150 ns Read Access Time (64 M)
Enhanced Data Protection Features
Absolute Protection with
V
PEN
= GND
Flexible Block Locking
Block Erase/Program Lockout
during Power Transitions
Industry-Standard Packaging
µBGA* Package (64 M), SSOP and
TSOP Packages (32 M)
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Cross-Compatible Command Support
Intel Basic Command Set
Common Flash Interface
Scaleable Command Set
32-Byte Write Buffer
6.3 µs per Byte Effective
Programming Time
6,400,000 Total Erase Cycles (64 M)
3,200,000 Total Erase Cycles (32 M)
100,000 Erase Cycles per Block
Automation Suspend Options
Block Erase Suspend to Read
Block Erase Suspend to Program
System Performance Enhancements
STS Status Output
Expanded Temperature Operation
–20 °C to +70 °C
Intel
®
StrataFlash™ Memory Flash
Technology
n
Capitalizing on two-bit-per-cell technology, Intel® StrataFlash™ memory products provide 2X the bits in 1X
the space. Offered in 64-Mbit (8-Mbyte) and 32-Mbit (4-Mbyte) densities, Intel StrataFlash memory devices
are the first to bring reliable, two-bit-per-cell storage technology to the flash market.
Intel StrataFlash memory benefits include: more density in less space, lowest cost-per-bit NOR devices,
support for code and data storage, and easy migration to future devices.
Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, Intel StrataFlash
memory devices take advantage of 400 million units of manufacturing experience since 1988. As a result,
Intel StrataFlash components are ideal for code or data applications where high density and low cost are
required. Examples include networking, telecommunications, audio recording, and digital imaging.
By applying FlashFile™ memory family pinouts, Intel StrataFlash memory components allow easy design
migrations from existing 28F016SA/SV, 28F032SA, and Word-Wide FlashFile memory devices (28F160S5
and 28F320S5).
Intel StrataFlash memory components deliver a new generation of forward-compatible software support. By
using the Common Flash Interface (CFI) and the Scaleable Command Set (SCS), customers can take
advantage of density upgrades and optimized write capabilities of future Intel StrataFlash memory devices.
Manufactured on Intel’s 0.4 micron ETOX™ V process technology, Intel StrataFlash memory provides the
highest levels of quality and reliability.
July 1998
Order Number: 290606-006
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F320J5 and 28F640J4 may contain design defects or errors known as errata. Current characterized errata are available
on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 8021-9808
or call 1-800-548-4725
or visit Intel’s website at http://www.intel.com
COPYRIGHT © INTEL CORPORATION 1997, 1998
CG-041493
*Third-party brands and names are the property of their respective owners.
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INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
®
CONTENTS
PAGE
PAGE
4.8 Write to Buffer Command ...........................28
4.9 Byte/Word Program Commands.................28
4.10 Configuration Command...........................29
4.11 Set Block and Master Lock-Bit
Commands................................................29
4.12 Clear Block Lock-Bits Command ..............30
5.0 DESIGN CONSIDERATIONS ........................40
5.1 Three-Line Output Control..........................40
5.2 STS and Block Erase, Program, and Lock-
Bit Configuration Polling ............................40
5.3 Power Supply Decoupling ..........................40
5.4 V
CC
, V
PEN
, RP# Transitions........................40
5.5 Power-Up/Down Protection ........................41
5.6 Power Dissipation.......................................41
6.0 ELECTRICAL SPECIFICATIONS..................42
6.1 Absolute Maximum Ratings ........................42
6.2 Operating Conditions..................................42
6.3 Capacitance ...............................................42
6.4 DC Characteristics .....................................43
6.5 AC Characteristics—Read-Only
Operations.................................................46
6.6 AC Characteristics— Write Operations.......48
6.7 Block Erase, Program, and Lock-Bit
Configuration Performance........................51
7.0 ORDERING INFORMATION..........................52
8.0 ADDITIONAL INFORMATION .......................53
1.0 PRODUCT OVERVIEW ...................................5
2.0 PRINCIPLES OF OPERATION .....................11
2.1 Data Protection ..........................................12
3.0 BUS OPERATION .........................................12
3.1 Read ..........................................................13
3.2 Output Disable ...........................................13
3.3 Standby......................................................13
3.4 Reset/Power-Down ....................................13
3.5 Read Query................................................14
3.6 Read Identifier Codes.................................14
3.7 Write ..........................................................14
4.0 COMMAND DEFINITIONS ............................14
4.1 Read Array Command................................18
4.2 Read Query Mode Command.....................18
4.2.1 Query Structure Output .......................18
4.2.2 Query Structure Overview ...................20
4.2.3 Block Status Register ..........................21
4.2.4 CFI Query Identification String.............22
4.2.5 System Interface Information...............23
4.2.6 Device Geometry Definition .................24
4.2.7 Primary-Vendor Specific Extended
Query Table .......................................25
4.3 Read Identifier Codes Command ...............26
4.4 Read Status Register Command................27
4.5 Clear Status Register Command................27
4.6 Block Erase Command ..............................27
4.7 Block Erase Suspend Command................27
PRELIMINARY
3
INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
®
E
REVISION HISTORY
Date of
Revision
09/01/97
09/17/97
12/01/97
Version
-001
-002
-003
Original Version
Modifications made to cover sheet
V
CC
/GND Pins Converted to No Connects specification change added
I
CCS
, I
CCD
, I
CCW
, and I
CCE
specification change added
Order Codes specification change added
The
µBGA*
chip-scale package in Figure 2 was changed to a 52-ball
package and appropriate documentation added. The 64-Mb
µBGA
package dimensions were changed in Figure 2. Changed Figure 4 to read
SSOP instead of TSOP.
32-Mbit Intel StrataFlash memory read access time added. The number
of block erase cycles was changed. The write buffer program time was
changed. The operating temperature was changed. A read parameter
was added. Several program, erase, and lock-bit specifications were
changed. Minor documentation changes were made as well. Datasheet
designation changed from Advance Information to Preliminary.
Intel StrataFlash memory 32-Mb
µBGA
package removed. t
EHEL
read
specification reduced. Table 4 was modified. The
Ordering Information
was updated.
Description
1/31/98
-004
3/23/98
-005
7/13/98
-006
4
PRELIMINARY
E
INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
Individual block locking uses a combination of bits,
block lock-bits and a master lock-bit, to lock and
unlock blocks. Block lock-bits gate block erase
and program operations while the master lock-bit
gates block lock-bit modification. Three lock-bit
configuration operations set and clear lock-bits
(Set Block Lock-Bit, Set Master Lock-Bit, and
Clear Block Lock-Bits commands).
The status register indicates when the WSM’s
block erase, program, or lock-bit configuration
operation is finished.
The STS (STATUS) output gives an additional
indicator of WSM activity by providing both a
hardware signal of status (versus software polling)
and status masking (interrupt masking for
background block erase, for example). Status
indication using STS minimizes both CPU
overhead and system power consumption. When
configured in level mode (default mode), it acts as
a RY/BY# pin. When low, STS indicates that the
WSM is performing a block erase, program, or
lock-bit configuration. STS-high indicates that the
WSM is ready for a new command, block erase is
suspended (and programming is inactive), or the
device is in reset/power-down mode. Additionally,
the configuration command allows the STS pin to
be configured to pulse on completion of
programming and/or block erases.
Three CE pins are used to enable and disable the
device. A unique CE logic design (see Table 2,
Chip Enable Truth Table
) reduces decoder logic
typically required for multi-chip designs. External
logic is not required when designing a single chip,
a dual chip, or a 4-chip miniature card or SIMM
module.
The BYTE# pin allows either x8 or x16 read/writes
to the device. BYTE# at logic low selects 8-bit
mode; address A
0
selects between the low byte
and high byte. BYTE# at logic high enables 16-bit
operation; address A
1
becomes the lowest order
address and address A
0
is not used (don’t care). A
device block diagram is shown in Figure 1.
When the device is disabled (see Table 2,
Chip
Enable Truth Table
) and the RP# pin is at V
CC
, the
standby mode is enabled. When the RP# pin is at
GND, a further power-down mode is enabled
which minimizes power consumption and provides
write protection during reset. A reset time (t
PHQV
)
is required from RP# switching high until outputs
®
1.0 PRODUCT OVERVIEW
The Intel
®
StrataFlash™ memory family contains
high-density memories organized as 8 Mbytes or
4 Mwords (64-Mbit) and 4 Mbytes or 2 Mwords
(32-Mbit). These devices can be accessed as 8- or
16-bit words. The 64-Mbit device is organized as
sixty-four 128-Kbyte (131,072 bytes) erase blocks
while the 32-Mbits device contains thirty-two 128-
Kbyte erase blocks. Blocks are selectively and
individually lockable and unlockable in-system.
See the memory map in Figure 5.
A Common Flash Interface (CFI) permits software
algorithms to be used for entire families of
devices. This allows device-independent, JEDEC
ID-independent, and forward- and backward-
compatible software support for the specified flash
device families. Flash vendors can standardize
their existing interfaces for long-term compatibility.
Scaleable Command Set (SCS) allows a single,
simple software driver in all host systems to work
with all SCS-compliant flash memory devices,
independent of system-level packaging (e.g.,
memory card, SIMM, or direct-to-board place-
ment). Additionally, SCS provides the highest
system/device data transfer rates and minimizes
device and system-level implementation costs.
A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine
(WSM) automatically executes the algorithms and
timings necessary for block erase, program, and
lock-bit configuration operations.
A block erase operation erases one of the device’s
128-Kbyte blocks typically within one second—
independent of other blocks. Each block can be
independently erased 100,000 times. Block erase
suspend mode allows system software to suspend
block erase to read or program data from any
other block.
Each device incorporates a Write Buffer of
32 bytes (16 words) to allow optimum
programming performance. By using the Write
Buffer, data is programmed in buffer increments.
This feature can improve system program
performance by up to 20 times over non Write
Buffer writes.
PRELIMINARY
5
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