ICS85322I
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
G
ENERAL
D
ESCRIPTION
The ICS85322I is a Dual LVCMOS / LVTTL-to-
Differential 2.5V / 3.3V LVPECL translator. The ICS85322I
has selectable single ended clock inputs. The single ended
clock input accepts LVCMOS or LVTTL input levels and
translate them to 2.5V / 3.3V LVPECL levels. The small
outline 8-pin SOIC package makes this device ideal for
applications where space, high performance and low power
are important.
F
EATURES
•
Two differential 2.5V/3.3V LVPECL outputs
•
Selectable CLK0, CLK1 LVCMOS/LVTTL clock inputs
•
CLK0 and CLK1 can accepts the following input levels:
LVCMOS or LVTTL
•
Maximum output frequency: 267MHz
•
Part-to-part skew: 250ps (maximum)
•
3.3V operating supply voltage
(operating range 3.135V to 3.465V)
•
2.5V operating supply voltage
(operating range 2.375V to 2.625V)
•
-40°C to 85°C ambient operating temperature
•
Available in standard (RoHS 5) or lead-free (RoHS 6)
packages
B
LOCK
D
IAGRAM
CLK0
Q0
nQ0
Q1
nQ1
P
IN
A
SSIGNMENT
Q0
nQ0
Q1
nQ1
1
2
3
4
8
7
6
5
V
CC
CLK0
CLK1
V
EE
CLK1
ICS85322I
8-Lead SOIC
3.90mm x 4.92mm x 1.37mm body package
M Package
Top View
85322AMI
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1
REV. D JULY 28, 2010
ICS85322I
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5
6
7
8
Name
Q0, nQ0
Q1, nQ1
V
EE
CLK1
CLK0
V
CC
Type
Output
Output
Power
Input
Input
Power
Pullup
Pullup
Description
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pin.
LVCMOS / LVTTL clock input.
LVCMOS / LVTTL clock input.
Positive supply pin.
NOTE:
Pullup
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
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2
REV. D JULY 28, 2010
ICS85322I
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5 V
50mA
100mA
112.7°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
25
Units
V
mA
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK0, CLK1
CLK0, CLK1
CLK0, CLK1
CLK0, CLK1
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
1.3
5
Units
V
V
µA
µA
T
ABLE
3C. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.65
Typical
Maximum
V
CC
- 0.9
V
CC
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
4A. AC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Par t-to-Par t Skew; NOTE 2, 3
Output Rise/Fall Time
20% to 80% @ 50MHz
300
ƒ
≤
267MHz
0.5
Test Conditions
Minimum
Typical
Maximum
267
1.9
250
700
Units
MHz
ns
ps
ps
t
sk(pp)
t
R
/ t
F
odc
Output Duty Cycle
40
60
%
All parameters measured at 133MHz unless noted otherwise.
NOTE 1: Measured from V
CC
/2 point of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
85322AMI
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3
REV. D JULY 28, 2010
ICS85322I
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
T
ABLE
3D. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
25
Units
V
mA
T
ABLE
3E. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK0, CLK1
CLK0, CLK1
CLK0, CLK1
CLK0, CLK1
V
CC
= V
IN
= 2.625
V
CC
= V
IN
= 2.625
-150
Test Conditions
Minimum
1.6
-0.3
Typical
Maximum
V
CC
+ 0.3
0.9
5
Units
V
V
µA
µA
T
ABLE
3F. LVPECL DC C
HARACTERISTICS
,
V
CC
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.65
Typical
Maximum
V
CC
- 0.9
V
CC
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
4B. AC C
HARACTERISTICS
,
V
CC
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Par t-to-Par t Skew; NOTE 2, 3
Output Rise/Fall Time
20% to 80% @ 50MHz
300
ƒ
≤
215MHz
0.7
Test Conditions
Minimum
Typical
Maximum
215
2.1
250
700
Units
MHz
ns
ps
ps
t
sk(pp)
t
R
/ t
F
odc
Output Duty Cycle
40
60
%
All parameters measured at 133MHz unless noted otherwise.
NOTE 1: Measured from V
CC
/2 point of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65..
85322AMI
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4
REV. D JULY 28, 2010
ICS85322I
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
2V
2V
V
CC
Qx
SCOPE
V
CC
Qx
SCOPE
LVPECL
nQx
LVPECL
V
EE
nQx
V
EE
-1.3V ± 0.165V
-0.5V ± 0.125V
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
nQx
PART 1
Qx
nQy
PART 2
CLK0,
CLK1
nQ0, nQ1
Q0, Q1
Qy
t
sk(o)
t
PD
P
ART
-
TO
-P
ART
S
KEW
P
ROPAGATION
D
ELAY
nQ0, nQ1
80%
Clock
Outputs
80%
V
SW I N G
20%
t
R
t
F
20%
Q0, Q1
Pulse Width
t
PERIOD
odc =
t
PW
t
PERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
85322AMI
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
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REV. D JULY 28, 2010
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