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TL16C754
QUAD UART WITH 64-BYTE FIFO
SLLS279A – OCTOBER 1998 – REVISED OCTOBER 1999
D
D
D
D
D
D
D
D
D
D
D
ST16C654 Pin Compatible With Additional
Enhancements
Supports Up To 50-MHz Input Clock
(3 Mbps) for 5-V Operation
Supports Up To 35-MHz Input Clock
(2 Mbps) for 3.3-V Operation
64-Byte Transmit FIFO
64-Byte Receive FIFO With Error Flags
Programmable and Selectable Transmit and
Receive FIFO Trigger Levels for DMA and
Interrupt Generation
Programmable Receive FIFO Trigger Levels
for Software/Hardware Flow Control
Software/Hardware Flow Control
– Programmable Xon/Xoff Characters
– Programmable Auto-RTS and Auto-CTS
Optional Data Flow Resume by Xon Any
Character
DMA Signalling Capability for Both
Received and Transmitted Data
Supports 3.3-V or 5-V Supply
D
D
D
D
D
D
D
D
D
D
D
D
Characterized for Operation From –40°C to
85°C
Software Selectable Baud Rate Generator
Prescalable Provides Additional Divide by 4
Function
Fast Access 2 Clock Cycle IOR/IOW Pulse
Width
Programmable Sleep Mode
Programmable Serial Interface
Characteristics
– 5, 6, 7, or 8-Bit Characters
– Even, Odd, or No Parity Bit Generation
and Detection
– 1, 1.5, or 2 Stop Bit Generation
False Start Bit Detection
Complete Status Reporting Capabilities in
Both Normal and Sleep Mode
Line Break Generation and Detection
Internal Test and Loopback Capabilities
Fully Prioritized Interrupt System Controls
Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and CD)
NC
NC
DSRA
CTSA
DTRA
VCC
RTSA
INTA
CSA
TXA
IOW
TXB
CSB
INTB
RTSB
GND
DTRB
CTSB
DSRB
NC
NC – No internal connection
NC
CDA
RIA
RXA
GND
D7
D6
D5
D4
D3
D2
D1
D0
INTSEL
VCC
RXD
RID
CDD
NC
NC
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
PN PACKAGE
(TOP VIEW)
TL16C754PN
51
50
49
48
47
46
45
44
43
42
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NC
DSRD
CTSD
DTRD
GND
RTSD
INTD
CSD
TXD
IOR
TXC
CSC
INTC
RTSC
VCC
DTRC
CTSC
DSRC
NC
NC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
NC
NC
CDB
RIB
RXB
CLKSEL
NC
A2
A1
A0
XTAL1
XTAL2
RESET
RXRDY
TXRDY
GND
RXC
RIC
CDC
NC
Copyright
©
1999, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
TL16C754
QUAD UART WITH 64-BYTE FIFO
SLLS279A – OCTOBER 1998 – REVISED OCTOBER 1999
DSRA
CTSA
DTRA
VCC
RTSA
INTA
CSA
TXA
IOW
TXB
CSB
INTB
RTSB
GND
DTRB
CTSB
DSRB
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CDA
RIA
RXA
GND
D7
D6
D5
D4
D3
D2
D1
D0
INTSEL
VCC
RXD
RID
CDD
8 7
6
5 4 3 2
1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
TL16C754FN
53
52
51
50
49
48
47
46
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
FN PACKAGE
(TOP VIEW)
DSRD
CTSD
DTRD
GND
RTSD
INTD
CSD
TXD
IOR
TXC
CSC
INTC
RTSC
VCC
DTRC
CTSC
DSRC
NC – No internal connection
description
The TL16C754 is a quad universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs, automatic
hardware/software flow control, and data rates up to 3 Mbps. The TL16C754 offers enhanced features. It has
a transmission control register (TCR) that stores received FIFO threshold level to start/stop transmission during
hardware and software flow control. With the FIFO RDY register, the software gets the status of TXRDY/RXRDY
for all four ports in one access. On-chip status registers provide the user with error indications, operational
status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal
loopback capability allows onboard diagnostics.
The UART transmits data sent to it from the peripheral 8-bit bus on the TX signal and receives characters on
the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO
and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own
desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity
and 1, 1.5, or 2 stop bits. The receiver can detect break, idle or framing errors, FIFO overflow, and parity errors.
The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control
operations, and software flow control and hardware flow control capabilities.
The TL16C754 is available in 80-pin TQFP and 68-pin PLCC packages.
2
CDB
RIB
RXB
CLKSEL
NC
A2
A1
A0
XTAL1
XTAL2
RESET
RXRDY
TXRDY
GND
RXC
RIC
CDC
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
TL16C754
QUAD UART WITH 64-BYTE FIFO
SLLS279A – OCTOBER 1998 – REVISED OCTOBER 1999
Terminal Functions
TERMINAL
NAME
A0
A1
A2
CDA, CDB
CDC, CDD
NO.
PN
30
29
28
79, 23
39, 63
FN
34
33
32
9, 27
43, 61
I
I
I
I
Address bit 0 select. Internal registers address selection. Refer to Table 5 for Register Address Map.
Address bit 1 select. Internal registers address selection. Refer to Table 5 for Register Address Map
Address bit 2 select. Internal registers address selection. Refer to Table 5 for Register Address Map
Carrier detect (active low). These inputs are associated with individual UART channels A through
D. A low on these pins indicates that a carrier has been detected by the modem for that channel.
Clock select. CLKSEL selects the divide-by-1 or divide-by-4 prescalable clock. During the reset,
a logic 1 (VCC) on CLKSEL selects the divide-by-1 prescaler. A logic 0 (GND) on CLKSEL selects
the divide-by-4 prescaler. The value of CLKSEL is latched into MCR[7] at the trailing edge of RESET.
A logic 1 (VCC) on CLKSEL will latch a 0 into MCR[7]. A logic 0 (GND) on CLKSEL will latch a 1 into
MCR[7]. MCR[7] can be changed after RESET to alter the prescaler value.
Chip select A, B, C, and D (active low). These pins enable data transfers between the user CPU
and the TL16C754 for the channel(s) addressed. Individual UART sections (A, B, C, D) are
addressed by providing a low on the respective CSA through CSD pin.
Clear to send (active low). These inputs are associated with individual UART channels A through
D. A low on the CTS pins indicates the modem or data set is ready to accept transmit data from the
754. Status can be checked by reading MSR bit 4. These pins only affect the transmit and receive
operations when auto CTS function is enabled through the enhanced feature register (EFR) bit 7,
for hardware flow control operation.
Data bus (bidirectional). These pins are the eight bit, 3-state data bus for transferring information
to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or
receive serial data stream.
Data set ready (active low). These inputs are associated with individual UART channels A through
D. A low on these pins indicates the modem or data set is powered on and is ready for data exchange
with the UART.
Data terminal ready (active low). These outputs are associated with individual UART channels A
through D. A low on these pins indicates that the 754A is powered on and ready. These pins can
be controlled through the modem control register. Writing a 1 to MCR bit 0 sets the DTR output to
low, enabling the modem. The output of these pins is high after writing a 0 to MCR bit 0, or after a
reset.
Signal and power ground
Interrupt A, B, C, and D (active high). These pins provide individual channel interrupts, INTA–D.
INTA–D are enabled when MCR bit 3 is set to a 1, interrupts are enabled in the interrupt enable
register (IER) and when an interrupt condition exists. Interrupt conditions include: receiver errors,
available receiver buffer data, transmit buffer empty, or when a modem status flag is detected.
INTA–D are in the high-impedance state after reset.
Interrupt select (active high with internal pulldown). INTSEL can be used in conjunction with MCR
bit 3 to enable or disable the 3-state interrupts INTA–D or override MCR bit 3 and force continuous
interrupts. Interrupt outputs are enabled continuously by making this pin a 1. Driving this pin low
allows MCR bit 3 to control the 3-state interrupt output. In this mode, MCR bit 3 is set to a 1 to enable
the 3-state outputs.
Read input (active low strobe). A valid low level on IOR will load the contents of an internal register
defined by address bits A0–A2 onto the TL16C754 data bus (D0–D7) for access by an external
CPU.
Write input (active low strobe). A valid low level on IOW will transfer the contents of the data bus
(D0–D7) from the external CPU to an internal register that is defined by address bits A0–A2.
I/O
DESCRIPTION
CLKSEL
26
30
I
CSA, CSB
CSC, CSD
9, 13,
49, 53
16, 20,
50, 54
I
CTSA, CTSB
CTSC, CTSD
4, 18
44, 58
11, 25
45, 59
I
D0–D2
D3–D7
DSRA, DSRB
DSRC, DSRD
68–70,
71–75
3, 19
43, 59
66–68,
1–5
10, 26
44, 60
I/O
I
DTRA, DTRB
DTRC, DTRD
5, 17
45, 57
12, 24
46, 58
O
GND
16, 36,
56, 76
6, 23,
40, 57
Pwr
INTA, INTB
INTC, INTD
8, 14,
48, 54
15, 21,
49, 55
O
INTSEL
67
65
I
IOR
51
52
I
IOW
11
18
I
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DALLAS, TEXAS 75265
3
TL16C754
QUAD UART WITH 64-BYTE FIFO
SLLS279A – OCTOBER 1998 – REVISED OCTOBER 1999
Terminal Functions (Continued)
TERMINAL
NAME
NO.
PN
33
FN
37
I
Reset. RESET will reset the internal registers and all the outputs. The UART transmitter output
and the receiver input will be disabled during reset time. See TL16C754 external reset conditions
for initialization details. RESET is an active high input.
Ring indicator (active low). These inputs are associated with individual UART channels A through
D. A low on these pins indicates the modem has received a ringing signal from the telephone line.
A low to high transition on these input pins generates an modem status interrupt, if it is enabled.
Request to send (active low). These outputs are associated with individual UART channels A
through D. A low on the RTS pins indicates the transmitter has data ready and waiting to send.
Writing a 1 in the modem control register (MCR bit 1) sets these pins to low, indicating data is
available. After a reset, these pins are set to 1. These pins only affects the transmit and receive
operation when auto RTS function is enabled through the enhanced feature register (EFR) bit 6,
for hardware flow control operation.
Receive data input. These inputs are associated with individual serial channel data to the 754A.
During the local loopback mode, these RX input pins are disabled and TX data is internally
connected to the UART RX input internally.
Receive ready (active low). RXRDY contains the wire-ORed status of all four receive channel
FIFOs, RXRDY A–D. It goes low when the trigger level has been reached or a timeout interrupt
occurs. It goes high when all RX FIFOs are empty and there is an error in RX FIFO.
Transmit data. These outputs are associated with individual serial transmit channel data from the
754A. During the local loopback mode, the TX input pin is disabled and TX data is internally
connected to the UART RX input.
Transmit ready (active low). TXRDY contains the wire-ORed status of all four transmit channel
FIFOs, TXRDY A–D. It goes low when there are a trigger level number of spares available. It goes
high when all four TX buffers are full.
Power supply inputs
Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input.
A crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see
Figures 10 and 11). Alternatively, an external clock can be connected to XTAL1 to provide custom
data rates.
Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal
oscillator output or buffered clock output.
I/O
DESCRIPTION
RESET
RIA, RIB
RIC, RID
78, 24
38, 64
8, 28
42, 62
I
RTSA, RTSB
RTSC, RTSD
7, 15
47, 55
14, 22
48, 56
O
RXA, RXB
RXC, RXD
77, 25
37, 65
7, 29
41, 63
I
RXRDY
34
38
O
TXA, TXB
TXC, TXD
10, 12
50, 52
17, 19
51, 53
O
TXRDY
35
6, 46,
66
39
13, 47,
64
O
VCC
Pwr
XTAL1
31
35
I
XTAL2
32
36
O
4
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