TMPR3907F
TOSHIBA RISC PROCESSOR
TENTATIVE
TMPR3907F
32-Bit TX System RISC
1. GENERAL DESCRIPTION
The TMPR3907F (TX3907) is a TX39 family microprocessor incorporating a 32-bit TX39/H core developed by Toshiba.
Designed for use in OA equipment, the TX3907 also incorporates such peripheral circuits as a memory controller, a PCI
controller, and timers.
2. FEATURES
TX39/H core
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An original Toshiba core based on the R3000A architecture of MIPS Technologies, Inc. of the United
States.
Instruction cache: 4 KB; data cache: 1 KB
Two banks x three channels
Supports Fast Page and Hyper Page (EDO) modes.
One bank x five channels (in Half-Speed Bus mode: three channels)
Supports mask ROM, Page mode ROM, EPROM, E
2
PROM, flash ROM, and SRAM.
Compliance with PCI Local Bus Specification Revision 2.1.
Initiator/target/arbiter
Five internal interrupts; three external interrupts
24-bit up-counter: three channels (one channel usable as a watchdog timer)
UART: one channel
DRAM address/ROM address/data separate bus
16-bit Data Bus and Half-Speed Bus modes (1/2 bus frequency) selectable
5 V tolerant input (data bus)
DRAM controller
ROM controller
PCI controller
Interrupt controller
Timers
Serial I/O
Bus interface
Power supply: 3.3 V
Maximum operating frequency: 66 MHz (PCI: 33 MHz)
Power dissipation: 800 mW (typ.)
Package: 208-pin plastic QFP
* R3000A is the trademark of MIPS Technologies, Inc.
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TOSHIBA continually is working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in
general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the
buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a
TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that
TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep
in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.
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The products described in this document are subject to foreign exchange and foreign trade laws.
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The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use.
No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others.
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The information contained herein is subject to change without notice.
1998-07-01 1/29
TMPR3907F
TENTATIVE
3. SYSTEM CONFIGURATION
3.1
TX3907 BLOCK DIAGRAM
TX39/H core
TX39
I-Cache
D-Cache
WBU
APU
G-Bus I/F
DSU
DRAMA[12:0]
XIN
XOUT
PLLOFF*
SYSCLK
PCIAD[31:0]
CBE[3:0]
PAR
FRAME*
TRDY*
IRDY*
STOP*
DEVSEL*
REQ[2:0]*
GNT[2:0]*
PCICLK
PERR*
SERR*
IDSEL
PCIC
ROMC1
(2ch.)
G Bus
SCSC
(2ch.)
PLL
CG
DRAMC
(3ch.)
RAS[2:0][1:0]*
WE*
CASBE[3:0]*
ACK*
EBIF
WR*
LAST
*
/RD*
D[31:0]
TEST*
RESET*
NMI*
INT[2:0]
ROMA[23:2]
SPA[1:0]
LEAFB*,LEAFA*
CE[4:3]*/SCS[1:0]*
OE*
SWE*
CE[2:0]*
DRESET*/CTS*
DCLK
IRC
ROMC0
(3ch.)
G to IM Bridge
IM Bus
TMR2
TMR1
TMR0
SIO
DS
MUX
DBGE*
PCST[2]
PCST[1]/SOUT
PCST[0]/RTS*
SDI/SIN
SDAO
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TMPR3907F
TENTATIVE
4. PIN DESCRIPTION
4.1
PIN ASSIGNMENT
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal Name
INT[1]
INT[0]
GNT[2]*
GNT[1]*
GNT[0]*
ROMA[23]
ROMA[22]
CE[4]*/SCS[1]*
VDD
VDD
VSS
CE[3]*/SCS[0]*
CE[2]*
CE[1]*
VSS
CE[0]*
SWE*
WR*
SPA[0]
SPA[1]
ROMA[2]
ROMA[3]
ROMA[4]
ROMA[5]
VDD
VSS
VSS
ROMA[6]
ROMA[7]
ROMA[8]
Pin No.
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Signal Name
ROMA[9]
OE*
SYSCLK
ACK*
LAST*/RD*
VDD
VSS
VSS
ROMA[10]
ROMA[11]
ROMA[12]
ROMA[13]
VDD
ROMA[14]
ROMA[15]
ROMA[16]
ROMA[17]
ROMA[18]
ROMA[19]
VSS
ROMA[20]
ROMA[21]
LEAFA*
LEAFB*
D[16]
D[24]
D[17]
D[25]
D[18]
VSS
Pin No.
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Signal Name
VDD
VSS
D[26]
D[19]
D[27]
DRAMA[0]
DRAMA[1]
DRAMA[2]
DRAMA[3]
DRAMA[4]
DRAMA[5]
VSS
VSS
VDD
DRAMA[6]
DRAMA[10]
D[20]
D[28]
D[21]
D[29]
D[22]
D[30]
D[23]
D[31]
VDD
VSS
DRAMA[7]
DRAMA[11]
DRAMA[8]
DRAMA[9]
Pin No.
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Signal Name
DRAMA[12]
RAS0[0]*
RAS0[1]*
RAS1[0]*
RAS1[1]*
VSS
VDD
RAS2[0]*
RAS2[1]*
CASBE[0]*
CASBE[1]*
CASBE[3]*
CASBE[2]*
WE*
D[0]
D[8]
PLLOFF*
PLL_VSS
VSS
XIN
XOUT
VDD
PLL_VDD
VDD
D[1]
D[9]
D[2]
D[10]
VSS
D[3]
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TMPR3907F
TENTATIVE
Pin No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
Signal Name
D[11]
D[4]
D[12]
D[13]
D[5]
D[14]
D[6]
D[15]
D[7]
VSS
VSS
RESET*
TEST*
NMI*
SDAO
DRESET*/CTS*
SDI/SIN
DBGE*
PCST[2]
PCST[1]/SOUT
PCST[0]/RTS*
VSS
Pin No.
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
Signal Name
DCLK
PCICLK
PCIAD[0]
PCIAD[1]
VDD
PCIAD[2]
PCIAD[3]
PCIAD[4]
PCIAD[5]
PCIAD[6]
PCIAD[7]
VDD
VSS
VSS
CBE[0]
PCIAD[8]
PCIAD[9]
PCIAD[10]
PCIAD[11]
PCIAD[12]
PCIAD[13]
VSS
Pin No.
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
Signal Name
VDD
PCIAD[14]
PCIAD[15]
CBE[1]
PAR
SERR*
PERR*
STOP*
VSS
DEVSEL*
TRDY*
IRDY*
FRAME*
CBE[2]
PCIAD[16]
PCIAD[17]
VDD
VSS
VSS
VDD
PCIAD[18]
PCIAD[19]
Pin No.
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
Signal Name
PCIAD[20]
PCIAD[21]
PCIAD[22]
PCIAD[23]
IDSEL
VSS
CBE[3]
PCIAD[24]
PCIAD[25]
PCIAD[26]
PCIAD[27]
PCIAD[28]
PCIAD[29]
VSS
VDD
VSS
PCIAD[30]
PCIAD[31]
REQ[2]*
REQ[1]*
REQ[0]*
INT[2]
The asterisk(*) after the signal name indicates active law.
1998-07-01 4/29
TMPR3907F
TENTATIVE
4.2
PIN FUNCTIONS
Signal Name
System interface signals
SYSCLK
O
System clock
Outputs the same clock as that of the TX39/H core (Full-Speed Bus mode) or half the
clock of the TX39/H core (Half-Speed Bus mode). Output can be halted using the
ROMA[20] pin at a reset.
CASBE[3:0]*
O
CAS / Byte Enable
Indicates the position of the valid data on the data bus D[31:0]. Operates as a CAS*
signal at DRAM access (including refresh cycle). In 16-bit Bus mode, CASBE[1:0]* only
is used.
The following shows the correspondence between CASBE[3:0] and the data bus.
CASBE[3]* D[31:24]
CASBE[2]* D[23:16]
CASBE[1]* D[15:8]
CASBE[0]* D[7:0]
D[31:0]
I/O
Data
Data bus.
In 16-bit Bus mode, D[15:0] is used.
LAST*/RD*
O
Last/Read
In Full-Speed Bus mode, functions as the LAST* signal, which indicates the end of bus
operation. In Half-Speed Bus mode, functions as the RD* signal, which indicates that the
bus operation in progress is a read.
WR*
O
Write
Indicates that the bus operation in progress is a write.
ACK*
I/O
Acknowledge
In Full-Speed Bus mode, functions as an output signal which indicates the completion of
the bus operation. In Half-Speed mode, operates as an input signal which completes the
SCS operation.
RESET*
I
Reset
Holding this signal low for at least 60 system clocks initializes the TX3907. The TX3907
is initialized in accordance with the ROMA[23:9] setting at a RESET* signal rising edge.
I/O
Function
1998-07-01 5/29
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