Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDSO16, 0.300 INCH, SOIC-16
| Parameter Name | Attribute value |
| Maker | Maxim |
| package instruction | SOP, |
| Reach Compliance Code | unknown |
| Other features | BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT |
| series | CMOS/TTL |
| Input frequency maximum value (fmax) | 1.38889 MHz |
| JESD-30 code | R-PDSO-G16 |
| JESD-609 code | e0 |
| length | 10.335 mm |
| Logic integrated circuit type | SILICON DELAY LINE |
| Number of functions | 1 |
| Number of taps/steps | 5 |
| Number of terminals | 16 |
| Maximum operating temperature | 70 °C |
| Minimum operating temperature | |
| Output polarity | TRUE |
| Package body material | PLASTIC/EPOXY |
| encapsulated code | SOP |
| Package shape | RECTANGULAR |
| Package form | SMALL OUTLINE |
| programmable delay line | NO |
| Certification status | Not Qualified |
| Maximum seat height | 2.68 mm |
| Maximum supply voltage (Vsup) | 5.25 V |
| Minimum supply voltage (Vsup) | 4.75 V |
| Nominal supply voltage (Vsup) | 5 V |
| surface mount | YES |
| technology | CMOS |
| Temperature level | COMMERCIAL |
| Terminal surface | TIN LEAD |
| Terminal form | GULL WING |
| Terminal pitch | 1.27 mm |
| Terminal location | DUAL |
| Total delay nominal (td) | 450 ns |
| width | 7.51 mm |
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