DC Output Current, per Pin ......................–25 mA to +25 mA
DC Input Voltage
[2]
.........................................–3.0V to +7.0V
DC Program Voltage................................................... +13.0V
Operating Range
Range
Commercial
Industrial
Military
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
–55
°
C to +125
°
C (Case)
Min.
2.4
0.45
2.2
–0.3
V
CC
+0.3
0.8
+10
+40
–90
150
170
200
220
100
100
V
CC
5V
±5%
5V
±10%
5V
±10%
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
mA
ns
ns
Electrical Characteristics
Over the Operating Range
[3]
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC1
I
CC2
t
R
t
F
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Level
Input LOW Level
Input Current
Output Leakage Current
Output Short Circuit Current
Power Supply
Current (Standby)
Power Supply Current
Recommended Input Rise Time
Recommended Input Fall Time
GND
≤
V
IN
≤
V
CC
V
O
= V
CC
or GND
V
CC
= Max., V
OUT
= 0.5V
[4, 5]
V
I
= V
CC
or GND (No
Load)
V
I
= V
CC
or GND (No
Load) f = 1.0 MHz
[4,6]
Commercial
Military/Industrial
Commercial
Military/Industrial
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8 mA
–10
–40
–30
Capacitance
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 2V, f = 1.0 MHz
V
OUT
= 2.0V, f = 1.0 MHz
Max.
10
10
Unit
pF
pF
AC Test Loads and Waveforms
[7]
5V
OUTPUT
50 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
R2
250Ω
R1 464Ω
5V
OUTPUT
5 pF
R2
250Ω
R1 464Ω
3.0V
GND
≤
6 ns
ALL INPUT PULSES
90%
10%
t
f
90%
10%
t
R
t
F
≤
6 ns
(a)
(b)
THÉVENIN EQUIVALENT (commercial/military)
163Ω
OUTPUT
1.75V
Notes:
2. Minimum DC input is –0.3V. During transitions, the inputs may undershoot to –2.0V for periods less than 20 ns.
3. Typical values are for T
A
= 25°C and V
CC
= 5V.
4. Guaranteed by design but not 100% tested.
5. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V
OUT
= 0.5V has been chosen to avoid
test problems caused by tester ground degradation.
6. Measured with device programmed as a 16-bit counter.
7. Part (a) in AC Test Load and Waveforms is used for all parameters except t
ER
and t
XZ
, which is used for part (b) in AC Test Load and Waveforms. All external timing
parameters are measured referenced to external pins of the device.
Document #: 38-03006 Rev. *B
Page 2 of 15
USE ULTRA37000
TM
FOR
ALL NEW DESIGNS
Timing Delays
Timing delays within the CY7C344 may be easily determined
using
Warp
®
,
Warp
Professional™, or
Warp
Enterprise™
software. The CY7C344 has fixed internal delays, allowing the
user to determine the worst case timing delays for any design.
CY7C344
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t
EXP
to t
S1
. Determine which of
1/(t
WH
+ t
WL
), 1/t
CO1
, or 1/(t
EXP
+ t
S1
) is the lowest frequency. The
lowest of these frequencies is the maximum data-path frequency for
the synchronous configuration.
When calculating external asynchronous frequencies, use
t
AS1
if all inputs are on dedicated input pins. If any data is applied to
an I/O pin, t
AS2
must be used as the required set-up time. If (t
AS2
+
t
AH
) is greater than t
ACO1
, 1/(t
AS2
+ t
AH
) becomes the limiting
frequency in the data-path mode unless 1/(t
AWH
+ t
AWL
) is less than
1/(t
AS2
+ t
AH
).
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t
EXP
to t
AS1
. Determine which
of 1/(t
AWH
+ t
AWL
), 1/t
ACO1
, or 1/(t
EXP
+ t
AS1
) is the lowest frequency.
The lowest of these frequencies is the maximum data-path frequency
for the asynchronous configuration.
The parameter t
OH
indicates the system compatibility of this device
when driving other synchronous logic with positive input hold times,
which is controlled by the same synchronous clock. If t
OH
is greater
than the minimum required input hold time of the subsequent
synchronous logic, then the devices are guaranteed to function
properly with a common synchronous clock under worst-case
environmental and supply voltage conditions.
The parameter t
AOH
indicates the system compatibility of this
device when driving subsequent registered logic with a positive hold
time and using the same clock as the CY7C344. In general, if t
AOH
is greater than the minimum required input hold time of the subse-
quent logic (synchronous or asynchronous), then the devices are
guaranteed to function properly under worst-case environmental and
supply voltage conditions, provided the clock signal source is the
same. This also applies if expander logic is used in the clock signal
path of the driving device, but not for the driven device. This is due to
the expander logic in the second device’s clock signal path adding an
additional delay (t
EXP
), causing the output data from the preceding
device to change prior to the arrival of the clock signal at the following
device’s register.
Design Recommendations
Operation of the devices described herein with conditions
above those listed under “Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this data sheet is not implied. Exposure to absolute maximum
ratings conditions for extended periods of time may affect
device reliability. The CY7C344 contains circuitry to protect
device pins from high-static voltages or electric fields; however,
normal precautions should be taken to avoid applying any
voltage higher than maximum rated voltages.
For proper operation, input and output pins must be
constrained to the range GND
≤
(V
IN
or V
OUT
)
≤
V
CC
. Unused
inputs must always be tied to an appropriate logic level (either V
CC
or
GND). Each set of V
CC
and GND pins must be connected together
directly at the device. Power supply decoupling capacitors of at least
0.2
µF
must be connected between V
CC
and GND. For the most
effective decoupling, each V
CC
pin should be separately decoupled.
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum
expander delay t
EXP
to the overall delay.
When calculating synchronous frequencies, use t
S1
if all inputs
are on the input pins. t
S2
should be used if data is applied at an I/O
pin. If t
S2
is greater than t
CO1
, 1/t
S2
becomes the limiting frequency
in the data-path mode unless 1/(t
WH
+ t
WL
) is less than 1/t
S2
.
EXPANDER
DELAY
t
EXP
LOGIC ARRAY
CONTROLDELAY t
CLR
t
LAC
t
PRE
INPUT
DELAY
t
IN
LOGIC ARRAY t
RSU
DELAY
t
RH
t
LAD
SYSTEM CLOCK DELAYt
ICS
I/O
I/O DELAY
t
IO
CLOCK
DELAY
t
IC
REGISTER
OUTPUT
DELAY
OUTPUT
t
COMB
t
LATCH
t
RD
t
OD
t
XZ
t
ZX
INPUT
I/O
FEEDBACK
DELAY
t
FD
Figure 1. CY7C344 Timing Model
Document #: 38-03006 Rev. *B
Page 3 of 15
USE ULTRA37000
TM
FOR
ALL NEW DESIGNS
External Synchronous Switching Characteristics
Over Operating Range
Parameter
t
PD1
t
PD2
t
PD3
t
PD4
t
EA
t
ER
t
CO1
t
CO2
t
S
t
H
t
WH
t
WL
t
RW
t
RR
t
RO
t
PW
t
PR
Description
Dedicated Input to Combinatorial Output Delay
I/O Input to Combinatorial Output Delay
[9]
Dedicated Input to Combinatorial Output Delay
with Expander Delay
[10]
I/O Input to Combinatorial Output Delay with
Expander Delay
[4, 11]
Input to Output Enable Delay
[4]
Input to Output Disable Delay
[4]
Synchronous Clock Input to Output Delay
Synchronous Clock to Local Feedback to
Combinatorial Output
[4, 12]
Dedicated Input or Feedback Set-Up Time to
Synchronous Clock Input
[8]
[7]
CY7C344
7C344-20
Min.
Max.
20
20
20
20
30
30
30
30
20
20
20
20
12
12
22
22
12
12
0
0
7
7
7
7
20
20
20
20
15
15
20
20
20
20
20
20
25
25
25
25
ns
15
15
0
0
8
8
8
8
25
25
25
25
25
25
ns
ns
ns
ns
ns
ns
ns
7C344-25
Min.
Max.
25
25
25
25
40
40
40
40
25
25
25
25
15
15
29
29
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
7C344-15
Min.
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Mil
Synchronous Clock Input HIGH Time
[4]
Synchronous Clock Input LOW Time
[4]
Asynchronous Clear Width
[4]
Asynchronous Clear Recovery
Time
[4]
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Asynchronous Clear to Registered Output
Delay
[4]
Asynchronous Preset
Width
[4]
Com’l/Ind
Mil
Com’l /Ind
Mil
Asynchronous Preset Recovery Time
[4]
Com’l /Ind
Mil
20
20
20
20
10
10
0
0
6
6
6
6
20
20
20
20
Max.
15
15
15
15
30
30
30
30
20
20
20
20
10
10
20
20
Input Hold Time from Synchronous Clock Input
[7]
Com’l/Ind
Notes:
8. This parameter is the delay from an input signal applied to a dedicated input pin to a combinatorial output on any output pin. This delay assumes no expander
terms are used to form the logic function.
9. This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to
form the logic function.
10. This parameter is the delay associated with an input signal applied to a dedicated input pin to combinatorial output on any output pin. This delay assumes
expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter
is tested periodically by sampling production material.
11. This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output pin. This delay assumes expander terms are used to
form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by
sampling production material.
12. This specification is a measure of the delay from synchronous register clock input to internal feedback of the register output signal to a combinatorial output for
which the registered output signal is used as an input. This parameter assumes no expanders are used in the logic of the combinatorial output and the register
is synchronously clocked. This parameter is tested periodically by sampling production material.
Document #: 38-03006 Rev. *B
Page 4 of 15
USE ULTRA37000
TM
FOR
ALL NEW DESIGNS
External Synchronous Switching Characteristics
Over Operating Range (continued)
[7]
7C344-15
Parameter
t
PO
t
CF
t
P
f
MAX1
f
MAX2
f
MAX3
f
MAX4
t
OH
Description
Asynchronous Preset to Registered Output
Delay
[4]
Com’l /Ind
Mil
Mil
External Synchronous Clock Period (1/f
MAX3
)
[4]
External Maximum Frequency(1/(t
CO1
+ t
S
))
[4, 14]
Maximum Frequency with Internal Only
Feedback (1/(t
CF
+ t
S
))
[4, 15]
Data Path Maximum Frequency, least of
1/(t
WL
+ t
WH
), 1/(t
S
+ t
H
), or (1/t
CO1
)
[4, 16]
Maximum Register Toggle Frequency
1/(t
WL
+ t
WH
)
[4, 17]
Output Data Stable Time from Synchronous
Clock Input
[4, 18]
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
13
13
50.0
50.0
71.4
71.4
83.3
83.3
83.3
83.3
3
3
Min.
Max.
15
15
4
4
14
14
41.6
41.6
62.5
62.5
71.4
71.4
71.4
71.4
3
3
7C344-20
Min.
Max.
20
20
4
4
CY7C344
7C344-25
Min.
Max.
25
25
7
7
16
16
33.3
33.3
45.4
45.4
62.5
62.5
62.5
62.5
3
3
ns
MHz
MHz
MHz
MHz
ns
ns
Unit
ns
Synchronous Clock to Local Feedback Input
[4, 13]
Com’l /Ind
Notes:
13. This specification is a measure of the delay associated with the internal register feedback path. This delay plus the register set-up time, t
S
, is the minimum internal
period for an internal state machine configuration. This parameter is tested periodically by sampling production material.
14. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external only feedback can operate.
15. This specification indicates the guaranteed maximum frequency at which a state machine with internal-only feedback can operate. If register output states must
also control external points, this frequency can still be observed as long as it is less than 1/t
CO1
. This specification assumes no expander logic is used. This parameter
is tested periodically by sampling production material.
16. This frequency indicates the maximum frequency at which the device may operate in data-path mode (dedicated input pin to output pin). This assumes that no
expander logic is used.
17. This specification indicates the guaranteed maximum frequency in synchronous mode, at which an individual output or buried register can be cycled by a clock
signal applied to either a dedicated input pin or an I/O pin.
18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.
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