CT2561
Bus Controller, Remote Terminal and BUS Monitor
FOR MIL-STD-1553B
Features
I
I
I
I
I
I
I
I
I
I
I
I
Second Source Compatible to the BUS-65610
16MHz CT2565 Replacement
RTU implements all dual redundant mode codes
Selective mode code illegalization available
16 bit microprocessor compatibility
BC checks status word for correct address and set flags
RTU illegal mode codes externally selectable
16 bit µProcessor compatibility
DMA handshaking for subsystem message transfers
Continuous On-Line and Initiated Built-In-Test
MIL-PRF-38534 compliant circuits available
Packaging – Hermetic Metal
• 78 Pin, 2.1" x 1.87" x .25" Plug-In type package
• 82 Lead, 2.2" x 1.61" x .18" Flat package
CIRCUIT TECHNOLOGY
www.aeroflex.com
A E
RO
F
LE
X
LA
C
ISO
9001
E
RT
I
F
I
E
D
B
S
I
NC
.
General Description
The CT2561 is a 16 MHz single chip dual redundant MIL-STD-1553 Bus Controller (BC), Remote
Terminal Unit (RTU) and Bus Monitor (MT). Packaged in a hybrid plug-in or flatpack, the CT2561
performs all the functions required to interface a MIL-STD-1553 dual redundant serial data bus such
as ACT4487 and a subsystem parallel three-state data bus.
Using a single Aeroflex custom monolithic ASIC design, the CT2561 features pin-for-pin and
functional CT2565 compatibility, user initiated self-test, and low power consumption.
Compatible with most microprocessors the CT2561 provides a 16bit three-state parallel data bus
and uses direct memory access (DMA type) handshaking for subsystem transfers. All message
transfer timing, DMA and control lines are provided internally, thereby reducing the subsystem
overhead associated with message transfers.
The CT2561 implements all dual redundant MIL-STD-1553 mode codes. In addition, any mode
code may (Optionally) be legalized through the use of an external PROM. Complete error detection
is provided by the CT2561 for BC and RTU operation. Error detection includes: response time-out,
inter-message gaps, sync, parity, Manchester, word count and bit count.
The CT2561 is fully compliant with MIL-STD-1553, is available screened in accordance with the
requirements of MIL-STD-883 and operates over the full military temperature range of -55°C to
+125°C.
eroflex Circuit T
echnology
– Data Bus Modules For The Future © SCDCT2561 REV A 8/16/99
STATUS INPUTS
Aeroflex Circuit Technology
RTADDR
DBACCEPT
SSFLAG
SERREQ
SSERR
SSBUSY
MODE CODE CONTROL
CH A
CONTROL
REMOTE
TERMINAL
LOGIC
TXINH A
TXDATA A
TXDATA A
RXDATA A
RXDATA A
CH A
ENCODE/
DECODE
WC0-WC4
T/R
LMC
ILLCMD
I/O0 - I/O16
DATA
BUFFERS
DATA BUS
BUFENA
R/W
EN
2
CH B
CONTROL
CONTROL BUS
BUS
CONTROLLER
LOGIC
I/O BUS
I/O LOGIC
BUFFERS
PARITY
CHECKER
TXINH
TXDATA
TXDATA
RXDATA
RXDATA
B
B
B
B
B
CH B
ENCODE/
DECODE
RTADDR
RTADR0
RTADR1
RTADR2
RTADR3
RTADR4
RTADRP
RTADDR
BUSREQ
BUSGRNT
BUSACK
TIMEOUT
SOM
EOM
INCMD
CS
OE
WR
TESTIN
TESTOUT
RT/BC
MT
BCSTART
CHA/CHB
LOOPERR
MSGERR
STATERR
LWORD
HSFAIL
STATEN
BITEN
NBGRNT
ADRINC
NODT
BSCTRCV
16MHz
SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700
Figure 1 – CT2561 Block Diagram
Table 1A – Pin Function Table (78 Pin Plug-In)
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Symbol
RT/BC
MT
STATEN
TIMEOUT
HSFAIL
DBACCEPT
SSFLAG
SVCREQ
INCMD
SSER
TESTOUT
WC1
WC3
TXINH B
T/R
CHA/CHB
CS
OE
BUSREQ
+5V
DB0(LSB)
DB2
DB4
DB6
DB8
DB10
DB12
DB14
I/O
I
I
O
O
O
I
I
I
O
I
-
O
O
O
O
O
O
O
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
Mode Select input - logic "1" for RT mode, logic “0” for BC mode.
Monitor mode enable. When unit is operating as a BC, a logic “0” will select
monitor mode.
Output signal in RT mode that indicates status word is being transferred on the
internal bus.
Indicates No Response Timeout has occurred during BC and RTU (RT to RT
transfer).
Output in RT mode indicating the DMA transfer did not occur in time to allow
proper operation on the 1553 bus.
Input signal used to set DBACCEPT bit in status register for response to a valid
mode command on the 1553 bus.
Input which controls the SSFLAG bit in the status register.
Input which controls the service request bit in the status word.
Output signal indicating the RT is currently in a message transfer sequence.
Input which controls the subsystem error bit in the status register.
Factory test point. Do not connect.
WC bit 1 - latched output of command word.
WC bit 3 - latched output of command word.
Transmitter inhibit output for channel B.
Output indicating T/R bit of current command word in RT mode.
Output indicating current selected channel (0 = Channel A).
Chip Select output for subsystem memory control.
Output Enable output for subsystem memory control.
Output signal used to initiate transfer to/from subsystem.
+5 Volt DC input.
Least significant bit - 16 bit parallel data bus.
Bit 2 of data bus.
Bit 4 of data bus.
Bit 6 of data bus.
Bit 8 of data bus.
Bit 10 of data bus.
Bit 12 of data bus.
Bit 14 of data bus.
Aeroflex Circuit Technology
3
SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700
Table 1A – Pin Function Table (78 Pin Plug-In) (continued)
Pin #
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Symbol
LWORD
MSGERR
TXDATA A
RXDATA A
RTADP
RTAD1
RTAD3
RESET
TXDATA B
RXDATA B
16MHz
GROUND
BCSTART
NBGRNT
BITEN
WR
BUSGRNT
LOOPERR
SSBUSY
ILLCMD
ADRINC
CHASSIS
WC0
WC2
WC4
TXINH A
LMC
TESTIN
I/O
-
O
O
I
I
I
I
I
O
I
I
-
I
O
O
O
I
O
I
I
O
-
O
O
O
O
O
-
Description
Last word output during BC mode indicates last data word of the current
message transfer has been transferred on the parallel bus.
Output signal which indicates an error occurred during the current message
sequence.
Bipolar serial data output to positive input of bus transceiver.
Bipolar serial input from negative output of bus transceiver.
Parity bit input for RT address.
Bit 1 of RT address input.
Bit 3 of RT address input.
System reset input - resets all inputs in module.
Bipolar serial data output to negative input bus transceiver.
Bipolar serial data input from positive output of bus transceiver.
16MHz TTL clock input.
Signal ground.
Cycle enable input Logic "0" initiates bus controller message transfer operation.
New bus grant output from RT indicates beginning of message transfer
sequence.
Built in Test enable output indicates RT is transferring BlT word on internal 16 bit
bus.
Write enable output for control of subsystem memory.
Bus request input in response to DTREQ. Allows BC/RT to transfer data to
subsystem.
Loop error output. Logic "0" indicates failure of loop back transmitted data.
Subsystem busy input for RT status word.
Illegal command input to RT, used to block RT response to an illegal command.
Increment output pulse. Goes LOW at the completion of each word transfer
to/from subsystem. Can increment external address counter.
Frame ground electricity isolated from signal ground
LSB of current command word count field.
Bit 2 of word count field.
Bit 4 of word count field.
Transmitter inhibit output signal for Channel A.
Latched Mode Command. Logic "1" indicates current word command is a mode
code word, WC0-WC4.
Factory test point. Do not connect.
Aeroflex Circuit Technology
4
SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700
Table 1A – Pin Function Table (78 Pin Plug-In) (continued)
Pin #
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
Symbol
EOM
BUFENA
BUSACK
DB1
DB3
DB5
DB7
DB9
DB11
DB13
DB15(MSB)
STATERR
TXDATA A
RXDATA A
NODT
RTAD0
RTAD2
RTAD4
BCSTRCV
TXDATA B
RXDATA B
SOM
I/O
O
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I
O
I
I
I
O
O
I
O
Description
End of message output. Logic "0" occurs when BC/RT message is completed.
Buffer enable input, may be driven LOW by STATEN or BITEN if subsystem
must read bit or Status words. Enables internal 16 bit bus onto subsystem bus.
Bus acknowledge output. LOW during DMA Handshake, in response to
BUSGRNT.
Bit 1 of 16 bit parallel bus.
Bit 3 of 16 bit parallel bus.
Bit 5 of 16 bit parallel bus.
Bit 7 of 16 bit parallel bus.
Bit 9 of 16 bit parallel bus.
Bit 11 of 16 bit parallel bus.
Bit 13 of 16 bit parallel bus.
Bit 15 of 16 bit parallel bus.
BC output indicates one or more bits set or address mismatch in a received
status word.
Bipolar serial data output to negative input of bus transceiver.
Bipolar serial data input from positive output of bus transceiver.
No data input. Logic "0" indicates the 1553 bus is idle; HIGH means device front
end is active.
LSB of 5 bit RT address.
Bit 2 of RT address.
Bit 4 of RT address.
Broadcast receive. Logic "0" means the current command was a broadcast
command.
Bipolar serial output to positive input of bus transceiver.
Bipolar serial input from negative output of bus transceiver.
Start of message output indicates beginning of RT/BC message transfer
sequence.
Aeroflex Circuit Technology
5
SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700
TI Technology Forum
京公网安备 11010802033920号
EEWORLD
