S71PL191H/193Hx0
Stacked Multi-Chip Product (MCP)
Flash Memory and SRAM/pSRAM
CMOS 3.0 Volt-only, Simultaneous Operation, Page Mode
Flash Memory and Static RAM/Pseudo-static RAM
Distinctive Characteristics
MCP Features
Power Supply Voltage of 2.7 to 3.1 V
High Performance
— Access time as fast as 70 ns
Packages
— 73-ball FBGA—9 x 13 mm
Operating Temperatures
— –25°C to +85°C
— –40°C to +85°C
ADVANCE
INFORMATION
General Description
The S71PL19xHx0 Series is a product line of stacked Multi-
Chip (MCP) Products and consists of
One S29PL127H or S29PL129H (Page mode,
Simultaneous Read/Write) Flash memory die
One S29JL064H (Simultaneous Read/Write)
32Mb or 64Mb PSRAM
The products covered in this document are
S71PL191HC0
S71PL191HB0
S71PL193HC0
S71PL193HB0
Their components are listed below. For details about their
specifications, please refer to the individual constituent data
sheets for further details.
128M Flash
S29PL127H
S29PL127H
S29PL129H
S29PL129H
64M Flash
S29JL064H
S29JL064H
S29JL064H
S29JL064H
PSRAM
32M
64M
32M
64M
MCP
S71PL191HB0
S71PL191HC0
S71PL193HB0
S71PL193HC0
Product Selector Guide
Flash Access
Time(ns)
70
70
70
70
pSRAM Access
Time (ns)
70
70
70
70
Device-Module#
S71PL191HB0Bxx10
S71PL193HB0Bxx10
S71PL191HC0Bxx00
S71PL193HC0Bxx00
pSRAM Density
32Mb
32Mb
64Mb
64Mb
Supplier
Supplier 2
Supplier 2
Supplier 1
Supplier 1
Package
FMB073
FMB073
FMB073
FMB073
Publication Number
S71PL191_193Hx0_00
Revision
A
Amendment
2
Issue Date
May 7, 2004
A d v a n c e
I n f o r m a t i o n
S71PL191H/193Hx0 1
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
MCP Block Diagram of S71PL191HB0 / S71PL193HB0 ..................................7
MCP Block Diagram of S71PL191HC0 / 193HC0 ...........................................8
Persistent Protection Bit Lock (PPB Lock) .............................................33
Dynamic Protection Bit (DYB) ...................................................................33
Sector Protection Schemes ................................................. 34
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 9
Connection Diagram of S71PL191HB0 .............................................................9
Connection Diagram of S71PL193HB0 .......................................................... 10
Connection Diagram of S71PL193HC0 ........................................................... 11
Connection Diagram of S71PL193HC0 .......................................................... 12
.............................................................................................................................. 12
Special Package Handling Instructions ...................................................... 12
Pin Description .................................................................................................13
Logic Symbol .................................................................................................... 14
Look-ahead Connection Diagram ...................................................................15
Special Package Handling Instructions .......................................................15
Persistent Sector Protection Mode Locking Bit ................................... 34
Password Protection Mode ............................................................................. 34
Password and Password Mode Locking Bit ............................................ 35
64-bit Password .............................................................................................. 35
Write Protect (WP#) ....................................................................................... 36
Persistent Protection Bit Lock ................................................................... 36
High Voltage Sector Protection ..................................................................... 36
In-System Sector Protection/
Sector Unprotection Algorithms ........................................... 37
Temporary Sector Unprotect ........................................................................ 38
Temporary Sector Unprotect Operation ................................. 38
SecSi™ (Secured Silicon) Sector Flash Memory Region .......................... 38
Factory-Locked Area (64 words) .............................................................. 39
Customer-Lockable Area (64 words) ...................................................... 39
SecSi Sector Protection Algorithm ........................................ 40
SecSi Sector Protection Bits ........................................................................ 41
SecSi Sector Protect Verify ................................................. 41
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 16
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 18
FMB073 ................................................................................................................... 18
S29PL127H/S29PL129H 1
Datasheet .................................................................................................................1
Distinctive Characteristics ..................................................................................1
Hardware Data Protection ..............................................................................41
Low VCC Write Inhibit ................................................................................. 41
Write Pulse “Glitch” Protection ............................................................... 42
Logical Inhibit ................................................................................................... 42
Power-Up Write Inhibit ............................................................................... 42
Common Flash Memory Interface (CFI) . . . . . . .42
CFI Query Identification String ............................................ 42
System Interface String ...................................................... 43
Device Geometry Definition ................................................. 43
Primary Vendor-Specific Extended Query .............................. 44
General Description . . . . . . . . . . . . . . . . . . . . . . . . 2
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .6
Simultaneous Operation Block Diagram . . . . . . . .7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . .9
S29PL127H/S29PL129H Device Bus Operations ....................... 9
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 45
Reading Array Data ........................................................................................... 45
Reset Command ................................................................................................. 45
Autoselect Command Sequence ....................................................................46
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence ..........................................................................................46
Word Program Command Sequence ...........................................................46
Unlock Bypass Command Sequence ........................................................ 47
Program Operation ............................................................ 48
Requirements for Reading Array Data ...........................................................9
Random Read (Non-Page Read) ..................................................................9
Page Mode Read .............................................................................................. 10
Page Select ...................................................................... 10
Simultaneous Operation ................................................................................... 10
Bank Select (S29PL127H) ................................................... 11
Bank Select (S29PL129H) ................................................... 11
................................................................................................................................... 11
Writing Commands/Command Sequences .................................................. 11
Accelerated Program Operation ................................................................ 11
Autoselect Functions ..................................................................................... 12
Standby Mode ........................................................................................................ 13
Automatic Sleep Mode .......................................................................................13
RESET#: Hardware Reset Pin ..........................................................................13
Output Disable Mode ........................................................................................ 14
S29PL127H Sector Architecture ........................................... 15
S29PL129H Sector Architecture ........................................... 22
SecSi
TM
Sector Addresses .................................................... 29
S29PL127H Boot Sector/Sector Block Addresses for Protection/
Unprotection ..................................................................... 30
S29PL129H Boot Sector/Sector Block Addresses for Protection/
Unprotection
CE1# Control .................................................................... 31
S29PL129H Boot Sector/Sector Block Addresses for Protection/
Unprotection
CE2# Control .................................................................... 31
Chip Erase Command Sequence ...................................................................48
Sector Erase Command Sequence ................................................................49
Erase Operation ................................................................ 50
Erase Suspend/Erase Resume Commands ..................................................50
Password Program Command ........................................................................ 51
Password Verify Command .............................................................................. 51
Password Protection Mode Locking Bit Program Command ............... 51
Persistent Sector Protection Mode Locking Bit Program Command 52
SecSi Sector Protection Bit Program Command ...................................... 52
PPB Lock Bit Set Command ............................................................................ 52
DYB Write Command ...................................................................................... 52
Password Unlock Command .......................................................................... 52
PPB Program Command .................................................................................. 53
All PPB Erase Command .................................................................................. 53
DYB Write Command ...................................................................................... 53
PPB Lock Bit Set Command ............................................................................ 53
PPB Status Command ....................................................................................... 54
PPB Lock Bit Status Command ...................................................................... 54
Sector Protection Status Command ............................................................ 54
Command Definitions Tables ..........................................................................55
Memory Array Command Definitions .................................... 55
Persistent Sector Protection ...........................................................................32
Persistent Protection Bit (PPB) ..................................................................32
Command Definitions Tables ..........................................................................56
May 7, 2004 S71PL191_193Hx0_00A2
3
A d v a n c e
I n f o r m a t i o n
Sector Protection Command Definitions ................................ 56
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 57
DQ7: Data# Polling ............................................................................................57
Data# Polling Algorithm ..................................................... 58
RY/BY#: Ready/Busy# ....................................................................................... 59
DQ6: Toggle Bit I ................................................................................................59
DQ2: Toggle Bit II ...............................................................................................59
Toggle Bit Algorithm .......................................................... 61
Simultaneous Read/Write Operations with Zero Latency ..................... 9
Standby Mode ....................................................................................................... 10
Automatic Sleep Mode ......................................................................................10
RESET#: Hardware Reset Pin ..........................................................................10
Output Disable Mode ......................................................................................... 11
S29JL064H Sector Architecture ............................................ 12
Bank Address .................................................................... 15
SecSi
TM
Sector Addresses ................................................... 15
Reading Toggle Bits DQ6/DQ2 ...................................................................... 61
DQ5: Exceeded Timing Limits ....................................................................... 62
DQ3: Sector Erase Timer ................................................................................ 62
Write Operation Status ....................................................... 63
Autoselect Mode ................................................................................................. 15
Sector/Sector Block Protection and Unprotection .................................. 16
S29JL064H Boot Sector/Sector Block Addresses for Protection/
Unprotection ..................................................................... 16
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .64
Maximum Negative Overshoot Waveform ............................. 64
Maximum Positive Overshoot Waveform ............................... 64
Write Protect (WP#) ........................................................................................18
WP#/ACC Modes ............................................................... 18
Temporary Sector Unprotect .........................................................................18
Temporary Sector Unprotect Operation ................................. 19
In-System Sector Protect/Unprotect Algorithms ..................... 20
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .65
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Test Setup ....................................................................... 66
Test Specifications ............................................................. 66
Input Waveforms and Measurement Levels ........................... 66
SecSi™ (Secured Silicon) Sector
Flash Memory Region ......................................................................................... 21
SecSi Sector Protect Verify ................................................. 22
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .67
Read-Only Operations – S29PL127H ............................................................67
Read-Only Operations –S29PL129H .............................................................67
Read Operation Timings ..................................................... 68
Page Read Operation Timings ............................................. 68
Hardware Data Protection ............................................................................. 22
Low VCC Write Inhibit ................................................................................ 22
Write Pulse “Glitch” Protection ............................................................... 23
Logical Inhibit ................................................................................................... 23
Power-Up Write Inhibit ............................................................................... 23
Hardware Reset (RESET#) .............................................................................. 69
Reset Timings ................................................................... 69
Common Flash Memory Interface (CFI) . . . . . . . 23
CFI Query Identification String ............................................ 24
System Interface String ...................................................... 24
Device Geometry Definition ................................................. 25
Primary Vendor-Specific Extended Query .............................. 26
Erase and Program Operations ..................................................................... 70
Program Operation Timings ................................................ 71
Accelerated Program Timing Diagram .................................. 71
Chip/Sector Erase Operation Timings ................................... 72
Back-to-back Read/Write Cycle Timings ............................... 73
Data# Polling Timings (During Embedded Algorithms) ............ 73
Toggle Bit Timings (During Embedded Algorithms) ................ 74
DQ2 vs. DQ6 .................................................................... 74
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 27
Reading Array Data ........................................................................................... 27
Reset Command ................................................................................................. 27
Autoselect Command Sequence ....................................................................28
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence ..........................................................................................28
Byte/Word Program Command Sequence .................................................28
Unlock Bypass Command Sequence ........................................................ 29
Program Operation ............................................................ 30
Temporary Sector Unprotect .........................................................................75
Temporary Sector Unprotect Timing Diagram ........................ 75
Sector/Sector Block Protect and
Unprotect Timing Diagram .................................................. 76
Alternate CE# Controlled Erase and Program Operations ..................77
Flash Alternate CE# Controlled Write (Erase/Program)
Operation Timings ............................................................. 78
Chip Erase Command Sequence ................................................................... 30
Sector Erase Command Sequence ................................................................. 31
Erase Operation ................................................................ 32
Erase And Programming Performance . . . . . . . .79
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . .80
Distinctive Characteristics .......................................................................... 80
Erase and Programming Performance ..................................................... 80
Latchup Characteristics ............................................................................... 80
Erase Suspend/Erase Resume Commands .................................................. 32
S29JL064H Command Definitions ........................................ 34
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 35
DQ7: Data# Polling ............................................................................................ 35
Data# Polling Algorithm ..................................................... 36
S29JL064H 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . 2
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . .7
S29JL064H Device Bus Operations ......................................... 7
RY/BY#: Ready/Busy# ........................................................................................37
DQ6: Toggle Bit I ............................................................................................... 37
Toggle Bit Algorithm .......................................................... 38
DQ2: Toggle Bit II .............................................................................................. 38
Reading Toggle Bits DQ6/DQ2 ..................................................................... 39
DQ5: Exceeded Timing Limits ........................................................................ 39
DQ3: Sector Erase Timer ................................................................................ 39
Write Operation Status ....................................................... 40
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 41
Maximum Negative Overshoot Waveform .............................. 41
Maximum Positive Overshoot Waveform ............................... 41
Word/Byte Configuration ..................................................................................8
Requirements for Reading Array Data ...........................................................8
Writing Commands/Command Sequences ...................................................8
Accelerated Program Operation .................................................................9
Autoselect Functions .......................................................................................9
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Wireless (W) Devices ................................................................................... 41
Industrial (I) Devices ...................................................................................... 41
V
CC
Supply Voltages ....................................................................................... 41
4
S71PL191_193Hx0_00A2 May 7, 2004
A d v a n c e
I n f o r m a t i o n
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .42
CMOS Compatible ............................................................................................ 42
Zero-Power Flash .............................................................................................43
I
CC1
Current vs. Time (Showing Active and
Automatic Sleep Currents) .................................................. 43
Typical I
CC1
vs. Frequency .................................................. 43
Test Setup ....................................................................... 44
Standby Mode Characteristic . . . . . . . . . . . . . . . .62
Recommended DC Operating Conditions . . . . . . 63
Capacitance (f = 1MHz, TA = +25°C) (Note 1) . . . 63
DC and Operating Characteristics . . . . . . . . . . . . 63
AC Operating Conditions . . . . . . . . . . . . . . . . . . . 63
Test Conditions (Test Load and Test Input/Output Reference) ......... 63
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Key To Switching Waveforms . . . . . . . . . . . . . . . 44
Input Waveforms and Measurement Levels ........................... 44
AC Characteristics (V
CC
=2.7~3.1V, T
A
=-40 to 85°C)
64
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . .64
Timing Waveform of Read Cycle(Note 1)(Address Controlled,
CS#=OE#=V
IL
, ZZ#=WE#=V
IH
, UB# or/and LB#=V
IL
) ......... 64
Timing Waveform of Read Cycle(Note 2)(ZZ#=WE#=V
IH
) ...... 65
Timing Waveform of Write Cycle (Note 1)(WE# Controlled,
ZZ#=V
IH
) ......................................................................... 65
Timing Waveform of Write Cycle (Note2)(CS# Controlled,
ZZ#=V
IH
) ......................................................................... 66
Timing Waveform of Write Cycle (Note3)(UB#, LB# Controlled,
ZZ#=V
IH
) ......................................................................... 66
Deep Power Down Mode ..................................................... 67
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .45
Read-Only Operations .....................................................................................45
Read Operation Timings ..................................................... 45
Hardware Reset (RESET#) .............................................................................. 46
Reset Timings ................................................................... 46
Word/Byte Configuration (BYTE#) ..............................................................47
BYTE# Timings for Read Operations ..................................... 48
BYTE# Timings for Write Operations .................................... 48
Erase and Program Operations ..................................................................... 49
Program Operation Timings ................................................ 50
Accelerated Program Timing Diagram .................................. 50
Chip/Sector Erase Operation Timings ................................... 51
Back-to-back Read/Write Cycle Timings ............................... 52
Data# Polling Timings (During Embedded Algorithms) ............ 52
Toggle Bit Timings (During Embedded Algorithms) ................ 53
DQ2 vs. DQ6 .................................................................... 53
64 Mb pSRAM (Supplier 1) 69
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Absolute Maximum Ratings . . . . . . . . . . . . . . . . .70
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .70
DC Recommended Operating Conditions (T
A
= -25°C to 85°C) . 70
DC Characteristics (T
A
= -25°C to 85°C, VDD = 2.6 to 3.3V) .... 71
Capacitance (T
A
= 25°C, f = 1 MHz) ..................................... 71
Temporary Sector Unprotect .........................................................................54
Temporary Sector Unprotect Timing Diagram ........................ 54
Sector/Sector Block Protect and
Unprotect Timing Diagram .................................................. 55
Alternate CE# Controlled Erase and Program Operations ..................56
Alternate CE# Controlled Write (Erase/Program) Operation Timings
57
Erase And Programming Performance . . . . . . . .58
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 58
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . .59
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 71
AC Characteristics and Operating Conditions (T
A
= -25°C to 85°C,
V
DD
= 2.6 to 3.3V) ............................................................ 71
AC Test Conditions ............................................................. 72
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Read Cycle ....................................................................... 73
Page Read Cycle (8 words access) ....................................... 74
Write Cycle 1 (WE# controlled) ........................................... 75
Write Cycle 2 (CE# controlled) ............................................ 76
Deep Power-down Timing ................................................... 76
Power-on Timing ............................................................... 76
Read Address Skew Provisions ............................................ 77
Write Address Skew Provisions ............................................ 77
32 Mb pSRAM (Supplier 2) 61
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . 61
Timing Waveform of Power Up . . . . . . . . . . . . . . 61
Timing Waveform (Power Up) ............................................. 61
Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .62
Absolute Maximum Ratings (Note 1) .................................... 62
Standby Mode State Machines . . . . . . . . . . . . . . .62
Standby Mode State Machines ............................................. 62
Revision Summary 79
May 7, 2004 S71PL191_193Hx0_00A2
5
A d v a n c e
I n f o r m a t i o n
Block Diagrams
MCP Block Diagram of S71PL191HB0 / S71PL193HB0
V
CC
A0 to A21
(A22 PL127H Only)
V
SS
A0 to A21 (A22)
CE#f1
CE#f2 (PL129H Only)
S29PL127H
or
S29PL129H
V
IO
= V
CC
DQ0 to DQ15
DQ0 to DQ1
V
CC
V
SS
A0 to A21
WP#/ACC
OE#
CE#f3
WE#
RESET#
S29JL064H
DQ0 to DQ15
V
SS
V
SSA
A0 to A20
32 Mb
pSRAM
V
CC
= V
CCQ
CE#1ps
CE2ps
UB#
LB#
DQ0 to DQ15
V
CC
V
SSQ
V
CCps
May 7, 2004 S71PL191_193Hx0_00A2
7
Embedded System
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