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Datasheet> All Categories > Discrete semiconductor> The transistor> RFG40N10LE
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RFG40N10LE

Description
Power Field-Effect Transistor, 40A I(D), 100V, 0.04ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-247,
CategoryDiscrete semiconductor    The transistor   
File Size478KB，8 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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RFG40N10LE Overview

Power Field-Effect Transistor, 40A I(D), 100V, 0.04ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-247,

RFG40N10LE Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Reach Compliance Codecompliant
ECCN codeEAR99
Shell connectionDRAIN
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage100 V
Maximum drain current (Abs) (ID)40 A
Maximum drain current (ID)40 A
Maximum drain-source on-resistance0.04 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JEDEC-95 codeTO-247
JESD-30 codeR-PSFM-T3
JESD-609 codee0
Number of components1
Number of terminals3
Operating modeENHANCEMENT MODE
Maximum operating temperature175 °C
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formFLANGE MOUNT
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Polarity/channel typeN-CHANNEL
Maximum power dissipation(Abs)150 W
Certification statusNot Qualified
surface mountNO
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal locationSINGLE
Maximum time at peak reflow temperatureNOT SPECIFIED
transistor applicationsSWITCHING
Transistor component materialsSILICON

RFG40N10LE Preview

RFG40N10LE, RFP40N10LE, RF1S40N10LESM
Data Sheet
January 2002
40A, 100V, 0.040 Ohm, Logic Level
N-Channel Power MOSFETs
These N-Channel enhancement mode power MOSFETs are
manufactured using the latest manufacturing process
technology. This process, which uses feature sizes
approaching those of LSI integrated circuits gives optimum
utilization of silicon, resulting in outstanding performance.
They were designed for use in applications such as
switching regulators, switching converters, motor drivers and
relay drivers. These transistors can be operated directly from
integrated circuits.
Formerly developmental type TA49163.
Features
• 40A, 100V
• r
DS(ON)
= 0.040
Ω
• Temperature Compensating PSPICE
®
Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175
o
C Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Ordering Information
PART NUMBER
RFG40N10LE
RFP40N10LE
RF1S40N10LESM
PACKAGE
TO-247
TO-220AB
TO-263AB
BRAND
FG40N10L
FP40N10L
F40N10LE
Symbol
D
G
NOTE: When ordering, use the entire part number. Add the suffix, 9A, to
obtain the TO-263AB variant in tape and reel, i.e. RF1S40N10LESM9A.
S
Packaging
JEDEC STYLE TO-247
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
DRAIN (FLANGE)
JEDEC TO-220AB
SOURCE
DRAIN
GATE
JEDEC TO-263AB
GATE
SOURCE
DRAIN
(FLANGE)
©2002 Fairchild Semiconductor Corporation
RFG40N10LE, RFP40N10LE, RF1S40N10LESM Rev. B
RFG40N10LE, RFP40N10LE, RF1S40N10LESM
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
RFG40N10LE, RFP40N10LE,
RF1S40N10LESM
100
100
±
10
40
Refer to Peak Current Curve
Refer to UIS Curve
150
1.00
-55 to 175
300
260
UNITS
V
V
V
A
Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
Drain to Gate Voltage (R
GS
= 20k
Ω)
(Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Gate to Source Voltage (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
D
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Single Pulse Avalanche Energy Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
pkg
W
W/
o
C
o
C
o
C
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 150
o
C.
Electrical Specifications
PARAMETER
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
I
DSS
I
GSS
r
DS(ON)
t
ON
t
d(ON)
t
r
t
d(OFF)
t
f
t
OFF
Q
g(TOT)
Q
g(5)
Q
g(TH)
C
ISS
C
OSS
C
RSS
R
θ
JC
R
θ
JA
All Packages
TO-247
TO-220AB and TO-263AB
V
GS
= 0V to 10V
V
GS
= 0V to 5V
V
GS
= 0V to 1V
V
DD
= 80V,
I
D
= 40A,
R
L
= 2.0
Ω
(Figures 20, 21)
TEST CONDITIONS
I
D
= 250
µ
A, V
GS
= 0V (Figure 13)
V
GS
= V
DS
, I
D
= 250
µ
A (Figure 12)
V
DS
= 95V, V
GS
= 0V
V
DS
= 90V, V
GS
= 0V, T
C
= 150
o
C
V
GS
=
±
10V
I
D
= 40A, V
GS
= 5V
V
DD
= 50V, I
D
= 40A, R
L
= 1.25
Ω
,
V
GS
= 5V, R
GS
= 2.5
Ω
(Figures 10, 18, 19)
MIN
100
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP
-
-
-
-
-
-
-
22
140
70
65
-
145
85
3
3000
500
200
-
-
-
MAX
-
3
1
250
10
0.040
200
-
-
-
-
165
180
105
4
-
-
-
1.0
30
80
UNITS
V
V
µ
A
µ
A
µ
A
Ω
ns
ns
ns
ns
ns
ns
nC
nC
nC
pF
pF
pF
o
C/W
o
C/W
o
C/W
Drain to Source Breakdown Voltage
Gate Threshold Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Drain to Source On Resistance (Note 2)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
Total Gate Charge
Gate Charge at 5V
Threshold Gate Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Thermal Resistance Junction-to-Case
Thermal Resistance Junction-to-Ambient
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
(Figure 14)
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Diode Reverse Recovery Time
NOTES:
2. Pulse test: pulse width
≤
80
µ
s, duty cycle
≤
2%.
3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
SYMBOL
V
SD
t
rr
I
SD
= 40A
I
SD
= 40A, dI
SD
/dt = 100A/
µ
s
TEST CONDITIONS
MIN
-
-
TYP
-
-
MAX
1.5
205
UNITS
V
ns
©2002 Fairchild Semiconductor Corporation
RFG40N10LE, RFP40N10LE, RF1S40N10LESM Rev. B
RFG40N10LE, RFP40N10LE, RF1S40N10LESM
Typical Performance Curves
1.2
POWER DISSIPATION MULTIPLIER
1.0
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125
T
C
, CASE TEMPERATURE (
o
C)
150
175
I
D
, DRAIN CURRENT (A)
Unless Otherwise Specified
50
40
30
20
10
0
25
50
75
100
125
150
175
T
C
, CASE TEMPERATURE (
o
C)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
1
Z
θJC
, NORMALIZED
THERMAL IMPEDANCE
0.5
0.2
0.1
0.1
0.05
0.02
0.01
SINGLE PULSE
0.01
10
-5
10
-4
10
-3
10
-2
10
-1
t, RECTANGULAR PULSE DURATION (s)
t
1
t
2
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θJC
x R
θJC
+ T
C
10
0
10
1
P
DM
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500
I
DM
, PEAK CURRENT CAPABILITY (A)
T
C
= 25
o
C
T
J
= 175
o
C
500
V
GS
= 10V
V
GS
= 5V
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
175
–
T
C
I = I 25
-----------------------
150
I
D
, DRAIN CURRENT (A)
100
100µs
100
10
1ms
10ms
THERMAL IMPEDANCE
MAY LIMIT CURRENT
IN THIS REGION
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
1
1
10
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
T
C
= 25
o
C
10
10
-5
10
-4
10
-3
10
-2
10
-1
t, PULSE WIDTH (s)
10
0
10
1
100
200
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
©2002 Fairchild Semiconductor Corporation
RFG40N10LE, RFP40N10LE, RF1S40N10LESM Rev. B
RFG40N10LE, RFP40N10LE, RF1S40N10LESM
Typical Performance Curves
500
I
AS
, AVALANCHE CURRENT (A)
If R = 0
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R
≠
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
STARTING T
J
= 25
o
C
Unless Otherwise Specified
(Continued)
80
I
D
, DRAIN CURRENT (A)
100
V
GS
= 10V
V
GS
= 5V
V
GS
= 4V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T
C
= 25
o
C
60
40
V
GS
= 3V
20
V
GS
= 2.5V
10
STARTING T
J
= 150
o
C
1
0.001
0.01
0.1
1
10
0
0
1.5
3.0
4.5
6.0
t
AV
, TIME IN AVALANCHE (ms)
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. SATURATION CHARACTERISTICS
I
DS(ON)
, DRAIN TO SOURCE CURRENT (A)
80
V
DD
= 15V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
-55
o
C
25
o
C
r
DS(ON)
, DRAIN TO SOURCE
ON RESISTANCE (mΩ)
175
o
C
100
I
D
= 10A
75
I
D
= 40A
I
D
= 80A
60
40
50
I
D
= 20A
25
PULSE DURATION = 80µs, V
DD
= 15V
DUTY CYCLE = 0.5% MAX.
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
20
0
0
1.5
3.0
4.5
6.0
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
GS
, GATE TO SOURCE VOLTAGE (V)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
700
V
DD
= 50V, I
D
= 40A, R
L
= 1.25Ω
600
SWITCHING TIME (ns)
500
400
300
200
t
d(OFF)
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
2.50
PULSE DURATION = 80µs,
DUTY CYCLE = 0.5% MAX.
V
GS
= 5V, I
D
= 40A
2.00
t
r
1.50
t
f
1.00
t
d(ON)
100
0
0
10
20
30
40
50
R
GS
, GATE TO SOURCE RESISTANCE (Ω)
0.50
0
-80
-40
0
40
80
120
160
200
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 10. SWITCHING TIME vs GATE RESISTANCE
FIGURE 11. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2002 Fairchild Semiconductor Corporation
RFG40N10LE, RFP40N10LE, RF1S40N10LESM Rev. B
RFG40N10LE, RFP40N10LE, RF1S40N10LESM
Typical Performance Curves
1.50
V
GS
= V
DS
, I
D
= 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
Unless Otherwise Specified
(Continued)
1.50
I
D
= 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
1.25
1.25
1.00
1.00
0.75
0.75
0.50
-80
-40
0
40
80
120
160
T
J
, JUNCTION TEMPERATURE (
o
C)
200
0.50
-80
-40
160
0
40
80
120
T
J
, JUNCTION TEMPERATURE (
o
C)
200
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
3500
C
ISS
2800
C, CAPACITANCE (pF)
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
≈
C
DS
+ C
GD
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
100
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
DD
= BV
DSS
75
R
L
= 2.5Ω
I
G(REF)
= 1.7mA
V
GS
= 5V
PLATEAU VOLTAGES IN
DESCENDING ORDER:
V
DD
= BV
DSS
V
DD
= 0.75 BV
DSS
V
DD
= 0.50 BV
DSS
V
DD
= 0.25 BV
DSS
I G
(
REF
)
I G
(
REF
)
V
DD
= BV
DSS
3.75
5.00
V
GS
, GATE TO SOURCE VOLTAGE (V)
2100
50
2.50
1400
25
1.25
700
C
OSS
C
RSS
0
20
---------------------
I G
(
ACT
)
t, TIME (µs)
80
---------------------
I G
(
ACT
)
0
0
0
5
10
15
20
25
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 15. SWITCHING WAVEFORMS FOR CONSTANT GATE
CURRENT
Test Circuits and Waveforms
V
DS
BV
DSS
L
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
V
GS
DUT
t
P
R
G
-
I
AS
V
DD
t
P
V
DS
V
DD
+
0V
I
AS
0.01Ω
0
t
AV
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
©2002 Fairchild Semiconductor Corporation
RFG40N10LE, RFP40N10LE, RF1S40N10LESM Rev. B
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RFG40N10LE Related Products

RFG40N10LE RFP40N10LE RF1S40N10LESM9A RF1S40N10LESM
Description Power Field-Effect Transistor, 40A I(D), 100V, 0.04ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-247, Power Field-Effect Transistor, 40A I(D), 100V, 0.04ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-220AB, Power Field-Effect Transistor, 40A I(D), 100V, 0.04ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB Power Field-Effect Transistor, 40A I(D), 100V, 0.04ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB
Is it Rohs certified? incompatible incompatible incompatible incompatible
Maker Fairchild Fairchild Fairchild Fairchild
Reach Compliance Code compliant compliant unknown unknown
ECCN code EAR99 EAR99 EAR99 EAR99
Shell connection DRAIN DRAIN DRAIN DRAIN
Configuration SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage 100 V 100 V 100 V 100 V
Maximum drain current (Abs) (ID) 40 A 40 A 40 A 40 A
Maximum drain current (ID) 40 A 40 A 40 A 40 A
Maximum drain-source on-resistance 0.04 Ω 0.04 Ω 0.04 Ω 0.04 Ω
FET technology METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR
JEDEC-95 code TO-247 TO-220AB TO-263AB TO-263AB
JESD-30 code R-PSFM-T3 R-PSFM-T3 R-PSSO-G2 R-PSSO-G2
JESD-609 code e0 e0 e0 e0
Number of components 1 1 1 1
Number of terminals 3 3 2 2
Operating mode ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE
Maximum operating temperature 175 °C 175 °C 175 °C 175 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form FLANGE MOUNT FLANGE MOUNT SMALL OUTLINE SMALL OUTLINE
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
Polarity/channel type N-CHANNEL N-CHANNEL N-CHANNEL N-CHANNEL
Maximum power dissipation(Abs) 150 W 150 W 150 W 150 W
Certification status Not Qualified Not Qualified Not Qualified Not Qualified
surface mount NO NO YES YES
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form THROUGH-HOLE THROUGH-HOLE GULL WING GULL WING
Terminal location SINGLE SINGLE SINGLE SINGLE
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
transistor applications SWITCHING SWITCHING SWITCHING SWITCHING
Transistor component materials SILICON SILICON SILICON SILICON

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[i=s]This post was last edited by qinyunti on 2022-12-15 13:47[/i]Some netizens are asking why PG2 doesn't light up. Here is an explanation. Because PG2 uses VDDIO2, its VDDIO2 power supply needs to b...
qinyunti stm32/stm8
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