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SL2309
Description
The SL2309 is a low skew, low jitter and low power Zero
Delay Buffer (ZDB) designed to produce up to nine (9)
clock outputs from one (1) reference input clock, for high
speed clock distribution applications.
The product has an on-chip PLL which locks to the input
clock at CLKIN and receives its feedback internally from
the CLKOUT pin.
The SL2309 has two (2) clock driver banks each with four
(4) clock outputs. These outputs are controlled by two (2)
select input pins S1 and S2. When only four (4) outputs
are needed, four (4) bank-B output clock buffers can be tri-
stated to reduce power dissipation and jitter. The select
inputs can also be used to tri-state both banks A and B or
drive them directly from the input bypassing the PLL and
making the product behave like a Non-Zero Delay Buffer
(NZDB).
The high-drive (-1H) version operates up to 140MHz and
low drive (-1) version operates up to 100MHz at 3.3V.
Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB)
Key Features
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10 to 140 MHz operating frequency range
Low output clock skew: 50ps-typ
Low output clock jitter:
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50 ps-typ cycle-to-cycle jitter
Low part-to-part output skew: 150 ps-typ
3.3 V power supply range
Low power dissipation:
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28 mA-max at 66 MHz
⎯
44 mA –max at 140 MHz
One input drives 9 outputs organized as 4+4+1
Select mode to bypass PLL or tri-state outputs
SpreadThru™ PLL that allows use of SSCG
Standard and High-Drive options
Available in 16-pin SOIC and TSSOP packages
Available in Commercial and Industrial grades
Printers and MFPs
Digital Copiers
PCs and Work Stations
DTV
Routers, Switchers and Servers
Digital Embeded Systems
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Applications
Benefits
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Up to nine (9) distribution of input clock
Standard and High-Dirive levels to control impedance
level, frequency range and EMI
Low power dissipation, jitter and skew
Low cost
Block Diagram
Low Pow er and
Low Jitter
P LL
C LKIN
MUX
CLK OU T
CLK A1
CLK A2
C LKA3
CLKA4
S2
Input Selection
Decoding Logic
S1
CLKB1
C LKB2
C LKB3
2
2
C LKB4
VD D
GN D
Rev 1.1, May 29, 2007
Page 1 of 12
2200 Laurelwood Road, Santa Clara, CA 95054 Tel: (408) 855-0555 Fax: (408) 855-0550 www.SpectraLinear.com
SL2309
Pin Configuration
16-Pin SOIC and TSSOP
Pin Description
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
CLKIN
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
S1
CLKB3
CLKB4
GND
VDD
CLKA3
CLKA4
CLKOUT
Pin Type
Input
Output
Output
Power
Power
Output
Output
Input
Input
Output
Output
Power
Power
Output
Output
Output
Pin Description
Reference Frequency Clock Input. Weak pull-down (250kΩ).
Buffered Clock Output, Bank A. Weak pull-down (250kΩ).
Buffered Clock Output, Bank A. Weak pull-down (250kΩ).
3.3V Power Supply.
Power Ground.
Buffered Clock Output, Bank B. Weak pull-down (250kΩ).
Buffered Clock Output, Bank B. Weak pull-down (250kΩ).
Select Input, select pin S2. Weak pull-up (250kΩ).
Select Input, select pin S1. Weak pull-up (250kΩ).
Buffered Clock Output, Bank B. Weak pull-down (250kΩ).
Buffered Clock Output, Bank B. Weak pull-down (250kΩ).
Power Ground.
3.3V Power Supply.
Buffered Clock Output, Bank A. Weak pull-down (250kΩ).
Buffered Clock Output, Bank A. Weak pull-down (250kΩ).
Buffered Clock Output, PLL Internal Feedback Output. Weak pull-down (250kΩ).
Rev 1.1, May 29, 2007
Page 2 of 12
SL2309
General Description
The SL2309 is a low skew, low jitter Zero Delay Buffer with
very low operating current.
The product includes an on-chip high performance PLL
that locks into the input reference clock and produces nine
(9) output clock drivers tracking the input reference clock
for systems requiring clock distribution.
in addition to CLKOUT that is used for internal PLL
feedback, there are two (2) banks with four (4) outputs in
each bank, bringing the number of total available output
clocks to nine (9).
Input and Output Frequency Range
The input and output frequency range is the same. But, it
depends on the drive and CL levels as given in the below
Table 1.
Drive
HIGH
HIGH
LOW
LOW
CL(pF)
15
30
15
30
Min(MHz)
10
10
10
10
Max(MHz)
140
100
100
66
Select Input Control
The SL2309 provides two (2) input select control pins
called S1 (Pin-9) and S2 (Pin-8). This feature enables
users to select various states of output clock banks-A and
bank-B, output source and PLL shutdown features as
shown in the Table 2.
The S1 (Pin-9) and S2 (Pin-8) inputs include 250 kΩ weak
pull-up resistors to VDD.
PLL Bypass Mode
If the S1 and S2 pins are logic Low(0) and High(1)
respectively, the on-chip PLL is shutdown and bypassed,
and all the nine output clocks bank A, bank B and
CLKOUT clocks are driven by directly from the reference
input clock. In this operation mode SL2309 works like a
non-ZDB fanout buffer. In this operation mode the input
power-down detection circuit is disabled and outputs
follow the input clock from DC to rated frequencies based
on drive levels and load specifications.
High and Low-Drive Product Options
The SL2309 is offered with High Drive “-1H” and Standard
Drive “-1” options. These drive options enable the users
to control load levels, frequency range and EMI. Refer to
the switching electrical tables for the details.
Skew and Zero Delay
All outputs should drive the similar load to achieve the
output-to-output skew and input-to-output specifications
given in the switching electrical tables. However, Zero
Delay between input and outputs can be adjusted by
changing the loading at CLKOUT relative to the banks A
and B clocks since CLKOUT is the feedback to the PLL.
Power Supply Range (VDD)
The SL2309 is designed to operate at VDD=3.3V (+/-
10%). An internal on-chip voltage regulator is used to
provide PLL constant power supply of 1.8V, leading to a
consistent and stable PLL electrical performance in terms
of skew, jitter and power dissipation.
Refer to SL23EP09 for 3.3V to 2.5V and SL23EPL09 for
1.8V power supply operations.
Table 1. Input/Output Frequency Range
If the input clock is DC (GND to VDD) or floating, this is
detected by an input frequency detection circuitry and all
nine (9) clock outputs are forced to Hi-Z. The PLL is
shutdown to save power. In this shutdown state, the
product draws less than 12μA-max supply current.
In PLL by-pass mode (S2=1 and S1=0), the detection
circuit is disabled and input frequency range is 10 to
100MHz for standard (-1) drive and 10 to 140MHz for high
(-1H) drive.
SpreadThru
™
Feature
If a Spread Spectrum Clock (SSC) were to be used as an
input clock, the SL2309 is designed to pass the
modulated Spread Spectrum Clock (SSC) signal from its
reference input to the output clocks. The same spread
characteristics at the input are passed through the PLL
and drivers without any degradation in spread percent
(%), spread profile and modulation frequency
Rev 1.1, May 29, 2007
Page 3 of 12
SL2309
S2
0
0
1
1
S1
0
1
0
1
Clock A1-A4
Tri-state
Driven
Driven
Driven
Clock B1-4
Tri-state
Tri-state
Driven
Driven
CLKOUT
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Status
On
On
Off
On
Table 2. Select Input Decoding
1500
1000
500
0
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
-500
-1000
-1500
Output Load Difference: FBK Load – CLKA or CLKB Load (pF)
Figure 1. CLKIN Input to CLK A and B Delay
(In terms of load difference between CLKOUT and CLK A and B)
Rev 1.1, May 29, 2007
Page 4 of 12
SL2309
Absolute Maximum Ratings
Description
Supply voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
ESD Rating (Human Body Model)
MIL-STD-883, Method 3015
In operation, C-Grade
In operation, I-Grade
No power is applied
In operation, power is applied
Condition
Min
– 0.5
– 0.5
0
– 40
– 65
–
–
2000
Max
4.6
VDD+0.5
85
85
150
125
260
–
Unit
V
V
°C
°C
°C
°C
°C
V
Operating Conditions:
Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades
Symbol
VDD
TA
Description
3.3V Supply Voltage
3.3V+/-10%
Condition
Min
3.0
0
– 40
–
Max
3.6
85
85
15
Unit
V
°C
°C
pF
Operating Temperature(Ambient) Commercial
Industrial
CLOAD
Load Capacitance
10 to 140 MHz, -1H high drive
All active PLL modes
10 to 100 MHz, -1H high drive
All active PLL modes
10 to 100MHz, -1 standard drive
All active PLL modes
10 to 66MHz, -1 standard drive
All active PLL modes
–
30
pF
–
15
pF
pF
–
–
0.05
30
7
100
CIN
tpu
Input Capacitance
Power-up Time
S1, S2 and CLKIN pins
Power-up time for all VDDs to reach
minimum VDD voltage (VDD=3.0V).
3.3V, (typical)
3.3V, (typical), -1H high drive
3.3V, (typical), -1 standard drive
pF
ms
CLBW
ZOUT
Closed-loop bandwidth
Output Impedance
1.2
22
32
MHz
Ω
Ω
Rev 1.1, May 29, 2007
Page 5 of 12
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