MBM29LV160TE12PCV datasheet, PDF

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MBM29LV160TE12PCV: DescriptionFlash, 2MX8, 120ns, PDSO48, PLASTIC, SOP-48; Categorystorage storage; File Size759KB，59 Pages; ManufacturerSPANSION; Websitehttp://www.spansion.com/

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MBM29LV160TE12PCV Overview

Flash, 2MX8, 120ns, PDSO48, PLASTIC, SOP-48

MBM29LV160TE12PCV Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SPANSION
Parts packaging code	SOIC
package instruction	PLASTIC, SOP-48
Contacts	48
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	120 ns
Spare memory width	8
startup block	TOP
command user interface	YES
Universal Flash Interface	YES
Data polling	YES
JESD-30 code	R-PDSO-C48
JESD-609 code	e0
length	10 mm
memory density	16777216 bit
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of departments/size	1,2,1,31
Number of terminals	48
word count	2097152 words
character code	2000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX8
Package body material	PLASTIC/EPOXY
encapsulated code	VSOC
Encapsulate equivalent code	TSSOC48,.4,16
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, VERY THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	3/3.3 V
Programming voltage	3 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	1 mm
Department size	16K,8K,32K,64K
Maximum standby current	0.000005 A
Maximum slew rate	0.035 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	C BEND
Terminal pitch	0.4 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
switch bit	YES
type	NOR TYPE
width	9.5 mm

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FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-20883-1E

FLASH MEMORY

CMOS

16M (2M

8/1M

16) BIT

MBM29LV160TE/BE

70/90/12

FEATURES

• 0.23

µm

Process Technology

• Single 3.0 V read, program and erase

Minimizes system level power requirements

• Compatible with JEDEC-standard commands

Uses same software commands as E

PROMs

• Compatible with JEDEC-standard world-wide pinouts

48-pin TSOP (I) (Package suffix: TN-Normal Bend Type, TR-Reversed Bend Type)

48-pin CSOP (Package suffix: PCV)

48-ball FBGA (Package suffix: PBT)

• Minimum 1,000,000 program/erase cycles

• High performance

70 ns maximum access time

• Sector erase architecture

One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode

One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode

Any combination of sectors can be concurrently erased. Also supports full chip erase

• Boot Code Sector Architecture

T = Top sector

B = Bottom sector

• Embedded Erase

Algorithms

Automatically pre-programs and erases the chip or any sector

(Continued)

PRODUCT LINE UP

Part No.

= 3.3 V

Ordering Part No.

= 3.0 V

Max. Address Access Time (ns)

Max. CE Access Time (ns)

Max. OE Access Time (ns)

+0.3 V

–0.3 V

+0.6 V

–0.3 V

MBM29LV160TE/160BE

—

120

MBM29LV160TE/BE

-70/90/12

GENERAL DESCRIPTION

The MBM29LV160TE/BE is a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M

words of 16 bits each. The MBM29LV160TE/BE is offered in a 48-pin TSOP (I), 48-pin CSOP and 48-ball FBGA

packages. The device is designed to be programmed in-system with the standard system 3.0 V V

supply. 12.0

V V

and 5.0 V V

are not required for write or erase operations. The device can also be reprogrammed in

standard EPROM programmers.

The standard MBM29LV160TE/BE offers access times of 70 ns, 90 ns and 120 ns, allowing operation of high-

speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable

(CE), write enable (WE), and output enable (OE) controls.

The MBM29LV160TE/BE is pin and command set compatible with JEDEC standard E

PROMs. Commands are

written to the command register using standard microprocessor write timings. Register contents serve as input

to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally

latch addresses and data needed for the programming and erase operations. Reading data out of the device is

similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29LV160TE/BE is programmed by executing the program command sequence. This will invoke the

Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths

and verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5 seconds.

Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase

Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed

before executing the erase operation. During erase, the device automatically times the erase pulse widths and

verifies proper cell margins.

Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.)

The device also features a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The MBM29LV160TE/BE is erased when shipped from the factory.

The device features single 3.0 V power supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low V

detector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ

by the Toggle Bit feature on DQ

, or the RY/BY output pin. Once the end of a program or erase cycle has been

comleted, the device internally resets to the read mode.

The MBM29LV160TE/BE also has a hardware RESET pin. When this pin is driven low, execution of any

Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then

reset to the read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset

occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically

reset to the read mode and will have erroneous data stored in the address locations being programmed or

erased. These locations need re-writing after the Reset. Resetting the device enables the system’s

microprocessor to read the boot-up firmware from the Flash memory.

Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest

levels of quality, reliability, and cost effectiveness. The MBM29LV160TE/BE memory electrically erases all bits

within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word

at a time using the EPROM programming mechanism of hot electron injection.

MBM29LV160TE12PCV Related Products

	MBM29LV160TE12PCV	MBM29LV160BE12PCV-E1	MBM29LV160BE12PBT-E1	MBM29LV160TE12PBT-E1	MBM29LV160TE12PBT	MBM29LV160TE12PCV-E1	MBM29LV160BE12PCV	MBM29LV160BE12PBT
Description	Flash, 2MX8, 120ns, PDSO48, PLASTIC, SOP-48	Flash, 2MX8, 120ns, PDSO48, PLASTIC, SOP-48	Flash, 2MX8, 120ns, PBGA48, PLASTIC, FBGA-48	Flash, 2MX8, 120ns, PBGA48, PLASTIC, FBGA-48	Flash, 2MX8, 120ns, PBGA48, PLASTIC, FBGA-48	Flash, 2MX8, 120ns, PDSO48, PLASTIC, SOP-48	Flash, 2MX8, 120ns, PDSO48, PLASTIC, SOP-48	Flash, 2MX8, 120ns, PBGA48, PLASTIC, FBGA-48
Parts packaging code	SOIC	SOIC	BGA	BGA	BGA	SOIC	SOIC	BGA
package instruction	PLASTIC, SOP-48	PLASTIC, SOP-48	PLASTIC, FBGA-48	PLASTIC, FBGA-48	PLASTIC, FBGA-48	PLASTIC, SOP-48	VSOC, TSSOC48,.4,16	TFBGA, BGA48,6X8,32
Contacts	48	48	48	48	48	48	48	48
Reach Compliance Code	compliant	compliant	unknown	unknown	compliant	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
Maximum access time	120 ns	120 ns	120 ns	120 ns	120 ns	120 ns	120 ns	120 ns
startup block	TOP	BOTTOM	BOTTOM	TOP	TOP	TOP	BOTTOM	BOTTOM
JESD-30 code	R-PDSO-C48	R-PDSO-C48	R-PBGA-B48	R-PBGA-B48	R-PBGA-B48	R-PDSO-C48	R-PDSO-C48	R-PBGA-B48
length	10 mm	10 mm	8 mm	8 mm	8 mm	10 mm	10 mm	8 mm
memory density	16777216 bit	16777216 bit	16777216 bit	16777216 bit	16777216 bit	16777216 bit	16777216 bit	16777216 bit
Memory IC Type	FLASH	FLASH	FLASH	FLASH	FLASH	FLASH	FLASH	FLASH
memory width	8	8	8	8	8	8	8	8
Number of functions	1	1	1	1	1	1	1	1
Number of terminals	48	48	48	48	48	48	48	48
word count	2097152 words	2097152 words	2097152 words	2097152 words	2097152 words	2097152 words	2097152 words	2097152 words
character code	2000000	2000000	2000000	2000000	2000000	2000000	2000000	2000000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
organize	2MX8	2MX8	2MX8	2MX8	2MX8	2MX8	2MX8	2MX8
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	VSOC	VSOC	TFBGA	TFBGA	TFBGA	VSOC	VSOC	TFBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE, VERY THIN PROFILE	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE, VERY THIN PROFILE	GRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	240	260	240	240	240	260	240	240
Programming voltage	3 V	3 V	3 V	3 V	3 V	3 V	3 V	3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1 mm	1 mm	1.2 mm	1.2 mm	1.2 mm	1 mm	1 mm	1.2 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
Nominal supply voltage (Vsup)	3 V	3 V	3 V	3 V	3 V	3 V	3 V	3 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	C BEND	C BEND	BALL	BALL	BALL	C BEND	C BEND	BALL
Terminal pitch	0.4 mm	0.4 mm	0.8 mm	0.8 mm	0.8 mm	0.4 mm	0.4 mm	0.8 mm
Terminal location	DUAL	DUAL	BOTTOM	BOTTOM	BOTTOM	DUAL	DUAL	BOTTOM
Maximum time at peak reflow temperature	30	40	30	30	30	40	30	30
type	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE
width	9.5 mm	9.5 mm	6 mm	6 mm	6 mm	9.5 mm	9.5 mm	6 mm
Is it Rohs certified?	incompatible	conform to	-	-	incompatible	conform to	incompatible	incompatible
Maker	SPANSION	SPANSION	-	-	-	SPANSION	SPANSION	SPANSION

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