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W3EG6466S265AD4SG

Description
DDR DRAM Module, 64MX64, 0.75ns, CMOS, ROHS COMPLIANT, SO-DIMM-200
Categorystorage    storage   
File Size210KB,13 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Environmental Compliance
Download Datasheet Parametric View All

W3EG6466S265AD4SG Overview

DDR DRAM Module, 64MX64, 0.75ns, CMOS, ROHS COMPLIANT, SO-DIMM-200

W3EG6466S265AD4SG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerMicrosemi
Parts packaging codeMODULE
package instructionDIMM,
Contacts200
Reach Compliance Codeunknown
ECCN codeEAR99
access modeDUAL BANK PAGE BURST
Maximum access time0.75 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-XDMA-N200
memory density4294967296 bit
Memory IC TypeDDR DRAM MODULE
memory width64
Number of functions1
Number of ports1
Number of terminals200
word count67108864 words
character code64000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize64MX64
Package body materialUNSPECIFIED
encapsulated codeDIMM
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
self refreshYES
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.3 V
Nominal supply voltage (Vsup)2.5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formNO LEAD
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
White Electronic Designs
W3EG6466S-AD4
-BD4
PRELIMINARY*
512MB – 2x32Mx64 DDR SDRAM UNBUFFERED, w/PLL
FEATURES
DDR200, DDR266 and DDR333
• JEDEC design specifications
Double-data-rate architecture
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Dual Rank
Power supply: 2.5V ± 0.20V
JEDEC standard 200 pin SO-DIMM package
• Package height options:
AD4: 35.5mm (1.38")
BD4: 31.75mm (1.25")
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
* This product is under development, is not qualified or characterized and is subject to
change without notice.
DESCRIPTION
The W3EG6466S is a 2x32Mx64 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of sixteen 32Mx8
components as eight 64Mx8 stacked DDR SDRAMs
in 66 pin TSOP packages mounted on a 200 pin FR4
substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
OPERATING FREQUENCIES
DDR333 @CL=2.5
Clock Speed
CL-t
RCD
-t
RP
166MHz
2.5-3-3
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 2
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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