Supertex inc.
P-Channel Enhancement-Mode
Lateral MOSFET
Features
►
►
►
►
►
►
►
Ultra-low threshold
High input impedance
Low input capacitance
Fast switching speeds
Low on-resistance
Freedom from secondary breakdown
Low input and output leakage
LP0701
General Description
These enhancement-mode (normally-off) transistors utilize
a lateral MOS structure and Supertex’s well-proven silicon-
gate manufacturing process. This combination produces
devices with the power handling capabilities of bipolar
transistors and with the high input impedance and negative
temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, these devices are free
from thermal runaway and thermally induced secondary
breakdown. The low threshold voltage and low on-resistance
characteristics are ideally suited for hand held, battery
operated applications.
Applications
►
►
►
►
►
►
Logic level interfaces
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Ordering Information
Part Number
LP0701LG-G
LP0701N3-G
LP0701N3-G P002
LP0701N3-G P003
LP0701N3-G P005
LP0701N3-G P013
LP0701N3-G P014
Package Options
8-Lead SOIC
TO-92
TO-92
TO-92
TO-92
TO-92
TO-92
Packing
2500/Reel
1000/Bag
2000/Reel
2000/Reel
2000/Reel
2000/Reel
2000/Reel
Product Summary
BV
DSS
/BV
DGS
-16.5V
R
DS(ON)
3.0kΩ
V
GS(TH)
-1.0V (max)
I
D(ON)
3.0mA (min)
Pin Configuration
D
D
D
D
DRAIN
NC
S
G
SOURCE
GATE
-G denotes a lead (Pb)-free / RoHS compliant package
NC
Refer to ‘P0xx’ Tape & Reel Specs for P002, P003, P005, P013, and P014
TO-92 Taping Specifications and Winding Styles
8-Lead SOIC
TO-92
Absolute Maximum Ratings
Parameter
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
Operating and storage temperature
Value
BV
DSS
BV
DGS
±10V
-55°C to +150°C
Product Marking
P0701
YYWW
LLLL
YY = Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
Package may or may not include the following marks: Si or
8-Lead SOIC
Si
LP
0 7 0 1
YYWW
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
YY = Year Sealed
WW = Week Sealed
= “Green” Packaging
Package may or may not include the following marks: Si or
TO-92
Doc.# DSFP-LP0701
B071513
Supertex inc.
www.supertex.com
LP0701
Thermal Characteristics
Package
8-Lead SOIC
TO-92
(continuous
)
(mA)
I
D
†
(pulsed)
(A)
I
D
†
Power Dissipation
@T
C
= 25 C
(W)
O
(
O
C/W)
θ
ja
(mA)
I
DR
I
DRM
†
(A)
-700
-500
-1.25
-1.25
1.5
‡
1.0
101
‡
132
-700
-500
-1.25
-1.25
Notes:
† I
D
(continuous) is limited by max rated T
j
.
‡ Mounted on FR4 board, 25mm x 25mm x 1.57mm
Electrical Characteristics
(T
= 25°C unless otherwise specified)
A
Sym
Parameter
Min
Typ
Max
Units
Conditions
BV
DSS
V
GS
ΔV
GS(th)
I
GSS
I
DSS
Drain-to-source breakdown voltage
Gate threshold voltage
Change in V
GS(th)
with temperature
Gate body leakage
Zero gate voltage drain current
-16.5
-0.5
-
-
-
-
-
-0.6
-1.25
-
-
-
-
500
-
-
-
-
-
-
-
-
-
-0.7
-
-
-
-
-0.4
-1.0
-2.30
2.0
1.7
1.3
-
700
120
100
40
-
-
-
-
-1.2
-
-1.0
-4.0
-100
-100
-1.0
-
-
-
4.0
2.0
1.5
0.75
-
250
125
60
20
20
30
30
-1.5
V
V
mV/
O
C
nA
nA
mA
A
V
GS
= 0V, I
D
= -1.0mA
V
GS
= V
DS
, I
D
= -1.0mA
V
GS
= V
DS
, I
D
= -1.0mA
V
GS
= ±10V, V
DS
= 0V
V
DS
= -15V, V
GS
= 0V
V
DS
= 0.8 Max Rating,
V
GS
= 0V, T
A
= 125
O
C
V
GS
= V
DS
= -2.0V
V
GS
= V
DS
= -3.0V
V
GS
= V
DS
= -5.0V
V
GS
= -2.0V, I
D
= -50mA
I
D(ON)
On-state drain current
R
DS(ON)
ΔR
DS(ON)
G
FS
C
ISS
C
OSS
C
RSS
t
d(ON)
t
r
t
d(OFF)
t
f
V
SD
Static drain-to-source on-state
resistance
Change in R
DS(ON)
with temperature
Forward transconductance
Input capacitance
Common source output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Diode forward voltage drop
Ω
%/
O
C
mmho
pF
V
GS
= -3.0V, I
D
= -150mA
V
GS
= -5.0V, I
D
= -300mA
V
GS
= -5.0V, I
D
= -300mA
V
GS
= -15V, I
D
= -1.0A
V
GS
= 0V,
V
DS
= -15V,
f = 1.0MHz
V
DD
= -15V,
I
D
= -1.25A,
R
GEN
= 25Ω
V
GS
= 0V, I
SD
= -500mA
ns
V
Notes:
1. All D.C. parameters 100% tested at 25
O
C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
Switching Waveforms and Test Circuit
0V
INPUT
-10V
10%
90%
t
(OFF)
t
r
t
d(OFF)
t
f
Pulse
Generator
R
GEN
D.U.T.
INPUT
t
(ON)
t
d(ON)
0V
OUTPUT
R
L
VDD
OUTPUT
VDD
Doc.# DSFP-LP0701
B071513
90%
10%
90%
10%
2
Supertex inc.
www.supertex.com
LP0701
Typical Performance Curves
-2.5
Output Characteristics
V
GS
= -5.0V
-2.5
Saturation Characteristics
V
GS
= -5.0V
-2.0
-4V
-2.0
I
D
(amperes)
-1.5
I
D
(amperes)
-1.5
-4V
-3V
-1.0
-3V
-1.0
-0.5
-2V
-1V
-0.5
-2V
-1V
0
-1
-2
0
0
-4
V
DS
(volts)
-8
-12
-16
0
V
DS
(volts)
-3
-4
-5
1.0
Transconductance vs. Drain Current
V
DS
= -15V
T
A
= -55
O
C
2
Power Dissipation vs. Case Temperature
0.8
SO-8
G
FS
(seimens)
P
D
(watts)
0.6
T
A
= 25
O
C
T
A
= 125 C
O
1
TO-92
0.4
0.2
0
0
I
D
(amperes)
Maximum Rated Safe Operating Area
-1.0
-2.0
0
0
25
50
75
100
125
150
T
C
( C)
O
-10
1.0
Thermal Response Characteristics
Thermal Resistance (normalized)
TO-92/SO-8 (pulsed)
I
D
(amperes)
-1.0
0.8
0.6
TO-92 (DC)
-0.1
SO-8 (DC)
0.4
TO-92
T
C
= 25V
P
D
= 1.0W
0.2
-0.01
-0.1
T
C
= 25
O
C
-1.0
V
DS
(volts)
-10
-100
0
0.001
0.01
0.1
1.0
10
t
p
(seconds)
Doc.# DSFP-LP0701
B071513
3
Supertex inc.
www.supertex.com
LP0701
Typical Performance Curves (cont.)
BV
DSS
Variation with Temperature
1.1
10
On-Resistance vs. Drain Current
V
GS
= -2.0V
V
GS
= -3.0V
V
GS
= -5.0V
8
BV
DSS
(normalized)
R
DSS(ON)
(ohms)
6
1.0
4
2
0.9
-50
0
50
100
150
0
0
-1
T
J
( C)
O
I
D
(amperes)
-2
-3
-2
Transfer Characteristics
V
DS
= -15V
1.4
V
(th)
and R
DS
Variation with Temperature
1.6
1.2
V
(th)
@ -1.0mA
1.4
I
D
(amperes)
T
A
= 25
O
C
-1
1.0
1.2
T
A
= 125
O
C
0.8
1.0
0.6
R
DS(ON)
@ -5V, -300mA
0.8
0
0
-1
-2
-3
-4
-5
0.4
-50
0
50
100
0.6
150
V
GS (volts)
Capacitance vs. Drain-to-Source Voltage
f = 1.0MHz
-8
T
J
(
O
C)
Gate Drive Dynamic Characteristics
V
DS
= -10V
-20V
238pF
-4
200
-10
C (picofarads)
100
C
OSS
C
RSS
0
V
GS
(volts)
C
ISS
-6
-2
0
-5
-10
-15
0
C
ISS
= 115pF
0
1
V
DS
(volts)
Q
G
(nanocoulombs)
2
3
4
5
Doc.# DSFP-LP0701
B071513
4
Supertex inc.
www.supertex.com
R
DS(ON)
(normalized)
V
GS(th)
(normalized)
T
A
= -55
O
C
LP0701
8-Lead SOIC (Narrow Body) Package Outline (LG)
D
8
Note 1
(Index Area
D/2 x E1/2)
θ1
E1
E
L2
Gauge
Plane
1
L
L1
θ
Seating
Plane
Top View
Note 1
A
h
A A2
A1
e
b
A
Seating
Plane
View B
h
View B
Side View
View A-A
Note:
1.
This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier;
an embedded metal marker; or a printed indicator.
Symbol
A
A1
A2
b
D
E
E1
e
h
L
L1
L2
θ
θ1
Dimension
(mm)
MIN
NOM
MAX
1.35*
-
1.75
0.10
-
0.25
1.25
-
1.65*
0.31
-
0.51
4.80* 5.80* 3.80*
4.90
6.00
3.90
5.00* 6.20* 4.00*
1.27
BSC
0.25
-
0.50
0.40
-
1.27
1.04
REF
0.25
BSC
0
O
-
8
O
5
O
-
15
O
JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005.
* This dimension is not specified in the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #:
DSPD-8SOLGTG, Version I041309.
Doc.# DSFP-LP0701
B071513
5
Supertex inc.
www.supertex.com
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