ALD-FREQ-D-K-P-A-T datasheet, PDF

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ALD-FREQ-D-K-P-A-T: DescriptionPECL Output Clock Oscillator, 0.75MHz Min, 800MHz Max, ROHS COMPLIANT, LOW PROFILE, CERAMIC, SMD, 6 PIN; CategoryPassive components oscillator; File Size2MB，3 Pages; ManufacturerAbracon; Websitehttp://www.abracon.com/index.htm; Environmental Compliance

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ALD-FREQ-D-K-P-A-T Overview

PECL Output Clock Oscillator, 0.75MHz Min, 800MHz Max, ROHS COMPLIANT, LOW PROFILE, CERAMIC, SMD, 6 PIN

ALD-FREQ-D-K-P-A-T Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Abracon
Reach Compliance Code	compliant
Other features	TRI-STATE; ENABLE/DISABLE FUNCTION; COMPLIMENTARY OUTPUT; TAPE AND REEL
maximum descent time	0.85 ns
Frequency Adjustment - Mechanical	NO
frequency stability	30%
Manufacturer's serial number	ALD
Installation features	SURFACE MOUNT
Maximum operating frequency	800 MHz
Minimum operating frequency	0.75 MHz
Maximum operating temperature	60 °C
Minimum operating temperature	-10 °C
Oscillator type	PECL
physical size	7.0mm x 5.0mm x 1.8mm
longest rise time	0.85 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %

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PECL/LVDS/CMOS OUTPUT SMD

CRYSTAL CLOCK OSCILLATOR

ALD SERIES

RoHS

Compliant

5.0 x 7.0 x 1.8mm

| | | | | | | | | | | | | | |

FEATURES:

• Based on a proprietary digital multiplier

• 2.5V to 3.3V +/- 5% operation

• Tri-State Output

• Ceramic SMD, low profile package

• Low Phase Noise and Jitter

•

156.25MHz, 187.5MHz, and 212.5MHz applications

APPLICATIONS:

• SONET, xDSL

• SDH, CPE

• STB

STANDARD SPECIFICATIONS:

PARAMETERS

ABRACON P/N:

Frequency range:

Operating temperature:

Storage temperature:

Overall frequency stability:

Supply voltage (Vdd):

Jitter (12KHz - 20MHz) =

Low Phase Noise:

ALD Series

750 kHz to 800 MHz

0° C to + 70° C (see options)

- 55° C to + 125° C

± 50 ppm max. (see options)

3.3V ±10% (see options)

RMS phase jitter 3ps typ., <5ps max.

period jitter < 35 ps peak to peak typical.

-109 dBc/Hz @ 1kHz Offset from 622.08MHz

-110 dBc/Hz @ 10kHz Offset from 622.08MHz

-109 dBc/Hz @ 100KHz Offset from 622.08MHz

-112 dBc/Hz @ 1kHz Offset from 155.52MHz

-125 dBc/Hz @ 10kHz Offset from 155.52MHz

-123 dBc/Hz @ 100KHz Offset from 155.52MHz

"1" (V

≥ 0.7*Vdd) or open: Oscillation

"0" (V

< 0.3*Vdd): No Oscillation / Hi Z

Tristate Function:

PECL:

Supply current (I

):25mA

max (for Fo<24MHz),65mA max (for 24MHz<Fo<96MHz) 100mA max (96MHz<Fo<700MHz)

Output Logic High:

-1.025V min, V

-0.880V max.

Output Logic Low:

-1.810V min. V

-1.620V max.

Symmetry (Duty Cycle):

45% min, 50% typ, 55% max,

Rise time:

0.85ns

Fall time:

0.85ns

Supply current (I

):25mA

max (for Fo<24MHz),45mA max (for 24MHz<Fo<96MHz),100mA max (96MHz<Fo<700MHz)

Output Clock Duty Cycle @ 1.25V:

45% min, 50% typical, 55% max

Output Differential Voltage (V

247mV min, 355mV typical, 454mV max

VDD Magnitude Change (∆V

-50mV min, 50mV max

Output High Voltage :

= 1.4V typical, 1.6V max.

Output Low Voltage:

= 0.9V min, 1.1V typical

Offset Voltage [R

= 100Ω]: V

= 1.125V min, 1.2V typical, 1.375V max

Offset Magnitude Change [R

= 100Ω]:

∆

= 0mV min, 3mV typical, 25mV max

Power-off Leakage (I

OXD

) [Vout=VDD or GND, VDD=0V] =

±1µA typical, ±10µA max.

Differential Clock Rise Time (t

) [R

=100Ω, CL=10pF]:

0.2nS min, 0.7nS typical, 1.0nS,max

Differential Clock Fall Time (t

) [R

=100Ω, CL=10pF]:

0.2nS min, 0.7nS typical, 1.0nS max

Supply current (I

):15mA

max (for Fo<24MHz),30mA max (for 24MHz<Fo<96MHz),40mA max (96MHz<Fo<700MHz)

Output Clock Rise/ Fall Time [10%~90% VDD with 10pF load]:

1.2ns typ, 1.6ns max.

Output Clock Duty Cycle [Measured @ 50% VDD]:

45% min, 50% typical, 55% max

LVDS

CMOS:

ABRACON IS

ISO 9001 / QS 9000

CERTIFIED

Revised: 08.18.09

30332

Esperanza, Rancho Santa Margarita, California

92688

tel 949-546-8000

fax 949-546-8001

| www.abracon.com

Visit www.abracon.com for Terms & Conditions of Sale

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