INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4050B
buffers
HEX non-inverting buffers
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
HEX non-inverting buffers
DESCRIPTION
The HEF4050B provides six non-inverting buffers with
high current output capability suitable for driving TTL or
high capacitive loads. Since input voltages in excess of the
buffers’ supply voltage are permitted, the buffers may also
be used to convert logic levels of up to 15 V to standard
TTL levels. Their guaranteed fan-out into common bipolar
logic elements is shown in the table below.
HEF4050B
buffers
Fig.2 Pinning diagram.
HEF4050BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4050BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4050BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
APPLICATION INFORMATION
Some examples of applications for the HEF4050B are:
•
LOCMOS to DTL/TTL converter
•
HIGH sink current for driving 2 TTL loads
Fig.1 Functional diagram.
•
HIGH-to-LOW level logic conversion
Input protection
Guaranteed fan-out in common logic families
DRIVEN ELEMENT
standard TTL
74 LS
74 L
GUARANTEED
FAN-OUT
2
9
16
Fig.4
Input protection circuit that allows input
voltages in excess of V
DD
.
FAMILY DATA, I
DD
LIMITS category BUFFERS
See Family Specifications
Fig.3 Logic diagram (one gate).
January 1995
2
Philips Semiconductors
Product specification
HEX non-inverting buffers
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C;
C
L
= 50 pF; input transition times
≤
20 ns
V
DD
V
Propagation delays
I
n
O
n
HIGH to LOW
LOW to HIGH
Output transition
times
HIGH to LOW
LOW to HIGH
5
10
15
5
10
15
5
10
15
5
10
15
t
TLH
t
THL
t
PLH
t
PHL
SYMBOL
TYP.
35
20
15
55
25
20
25
10
7
60
30
20
MAX.
70
35
30
110
55
40
50
20
14
120
60
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HEF4050B
buffers
TYPICAL EXTRAPOLATION
FORMULA
26 ns
+
(0,18 ns/pF) C
L
16 ns
+
(0,08 ns/pF) C
L
12 ns
+
(0,05 ns/pF) C
L
28 ns
+
(0,55 ns/pF) C
L
14 ns
+
(0,23 ns/pF) C
L
12 ns
+
(0,16 ns/pF) C
L
7 ns
+
(0,35 ns/pF) C
L
3 ns
+
(0,14 ns/pF) C
L
2 ns
+
(0,09 ns/pF) C
L
10 ns
+
(1,0 ns/pF) C
L
9 ns
+
(0,42 ns/pF) C
L
6 ns
+
(0,28 ns/pF) C
L
V
DD
V
Dynamic power
dissipation per
package (P)
5
10
15
TYPICAL FORMULA FOR P (µW)
3 800 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
11 600 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
65 900 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
where
f
i
= input freq. (MHz)
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
∑
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
January 1995
4
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