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Datasheet> All Categories > storage> storage> V59C1512164QAJ-37
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V59C1512164QAJ-37

Description
32MX16 DDR DRAM, 0.5ns, PBGA84, GREEN, MO-207, FBGA-84
Categorystorage    storage   
File Size1MB，74 Pages
ManufacturerProMOS Technologies Inc
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V59C1512164QAJ-37 Overview

32MX16 DDR DRAM, 0.5ns, PBGA84, GREEN, MO-207, FBGA-84

V59C1512164QAJ-37 Parametric

Parameter NameAttribute value
MakerProMOS Technologies Inc
Parts packaging codeDSBGA
package instructionGREEN, MO-207, FBGA-84
Contacts84
Reach Compliance Codeunknown
access modeFOUR BANK PAGE BURST
Maximum access time0.5 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-PBGA-B84
length12.5 mm
memory density536870912 bit
Memory IC TypeDDR DRAM
memory width16
Number of functions1
Number of ports1
Number of terminals84
word count33554432 words
character code32000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32MX16
Package body materialPLASTIC/EPOXY
encapsulated codeTFBGA
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE, FINE PITCH
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
width10 mm

V59C1512164QAJ-37 Preview

V59C1512(404/804/164)QA
HIGH PERFORMANCE 512 Mbit
DDR2 SDRAM
4 BANKS X 32Mbit X 4 (404)
4 BANKS X 16Mbit X 8 (804)
4 BANKS X 8Mbit X 16 (164)
5
DDR2-400
Clock Cycle Time (t
CK3
)
Clock Cycle Time (t
CK4
)
Clock Cycle Time (t
CK5
)
System Frequency (f
CK max
)
5ns
5ns
5ns
200 MHz
37
DDR2-533
5ns
3.75ns
3.75ns
266 MHz
PRELIMINARY
3
DDR2-667
5ns
3.75ns
3ns
333 MHz
Features
■
High speed data transfer rates with system frequency
up to 333 MHz
■
Posted CAS
■
Programmable CAS Latency: 3, 4 and 5
■
Programmable Additive Latency:0, 1, 2, 3 and 4
■
Write Latency=Read Latency-1
■
Programmable Wrap Sequence: Sequential
or Interleave
■
Programmable Burst Length: 4 and 8
Automatic and Controlled Precharge Command
■
Power Down Mode
■
Auto Refresh and Self Refresh
■
Refresh Interval: 7.8 us (8192 cycles/64 ms)
■
OCD (Off-Chip Driver Impendance Adjustment)
■
ODT (On-Die Termination)
■
Weak Strength Data-Output Driver Option
■
Bidirectional differential Data Strobe (Single-ended
data-strobe is an optional feature)
■
On-Chip DLL aligns DQ and DQs transitions with CK
transitions
■
Differential clock inputs CK and CK
■
JEDEC Power Supply 1.8V ± 0.1V
■
VDDQ=1.8V ± 0.1V
■
Available in 60-ball FBGA for x4 and x8 component or
84 ball FBGA for x16 component
■
PASR Partial Array Self Refresh
Available Speed Grade
-5 (DDR2-400) @CL3-3-3
-37 (DDR2-533) @CL4-4-4
-3 (DDR2-667) @CL5-5-5
Description
The V59C1512(404/804/164)QA is a four bank DDR
DRAM organized as 4 banks x 32Mbit x 4 (404), 4 banks x
16Mbit x 8 (804), or 4 banks x 8Mbit x 16 (164). The
V59C1512(404/804/164)QA achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output
data to a system clock.
The chip is designed to comply with the following key
DDR2 SDRAM features:(1) posted CAS with additive la-
tency, (2)write latency=read latency-1, (3)Off-chip Driv-
er(OCD) impedance adjustment, (4) On Die Termination.
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock. I/O
s are synchronized with a pair of bidirectional strobes
(DQS, DQS) in a source synchronous fashion.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A se-
quential and gapless data rate is possible depending on
burst length, CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
60 ball FBGA
84 ball FBGA
•
CK Cycle Time (ns)
-5
•
Power
Std.
•
-37
•
-3
•
L
•
Temperature
Mark
Blank
V59C1512(404/804/164)QA Rev.1.0 September 2005
1
ProMOS TECHNOLOGIES
DDR Part Number
V59C1512(404/804/164)QA
V
ProMOS
5 9
C
1
5 1 2 8 0
ORGANIZATION
& REFRESH
64Mx4, 8K : 25640
32Mx8, 8K : 25680
128Mx4, 8K : 51240
32Mx16, 8K : 51216
16Mx32, 8K : 51232
64Mx16, 8K : G0116
16Mx16, 8K : 25616
4
Q
A
F
5
TEMPERATURE
BLANK:
0 - 70C
-40 - 85C
-40 - 125C
TYPE
59 : DDR2
CMOS
64Mx8, 8K : 51280
256Mx4, 8K : G0140
128Mx8, 8K : G0180
I:
E:
SPEED
5 : 200MHz @CL3-3-3
37 : 266MHz @CL4-4-4
3 : 333MHz @CL5-5-5
25 : 400MHz @CL6-6-6
VOLTAGE
1:
1.8 V
BANKS
4 : 4 BANKS
8 : 8 BANKS
I/O
Q: SSTL_18
REV LEVEL
A: 1st
C: 3rd
F
B: 2nd D: 4th
PACKAGE
RoHS
GREEN PACKAGE
DESCRIPTION
J
FBGA
SPECIAL FEATURE
L : LOW POWER GRADE
U : ULTRA LOW POWER GRADE
* RoHS: Restriction of Hazardous Substances
* Green: RoHS-compliant and Halogen-free
512Mb Addressing
Confi gura tion
# of Bank
Bank Address
Auto precharge
Row Address
Column Address
128Mb x 4
4
BA0,BA1
A
10
/AP
A
0
~ A
13
A
0
~ A
9,
A
11
64Mb x 8
4
BA0,BA1
A
10
/AP
A
0
~ A
13
A
0
~ A
9
32Mb x1 6
4
BA0,BA1
A
10
/AP
A
0
~ A
12
A
0
~ A
9
V59C1512(404/804/164)QA Rev. 1.0 September 2005
2
ProMOS TECHNOLOGIES
V59C1512(404/804/164)QA
x4 pack age pinout (Top View) : 60ball FBGA Package
1
VDD
NC
2
NC
VSSQ
3
VSS
DM
VDDQ
DQ3
VSS
WE
BA1
A1
A5
A9
NC
A
B
C
D
E
F
G
H
J
K
L
7
VSSQ
DQS
VDDQ
DQ2
DQS
VSSQ
DQ0
VSSQ
8
9
VDDQ
NC
VDDQ
NC
VDD
ODT
VDDQ DQ1
NC
VSSQ
VDDL VREF
CKE
NC
BA0
A10
VSS
A3
A7
VDD
A12
VSSDL CK
RAS
CAS
A2
A6
A11
NC
CK
CS
A0
A4
A8
A13
VDD
VSS
Notes:
B1, B9, D1, D9 = NC for x4 organization.
Pins B3 has identical capacitance as pins B7.
VDDL and VSSDL are power and ground for the DLL. It is recommended that they are isolated on the device from
VDD, VDDQ, VSS, and VSSQ.
Ball Locations (x4)
: Populated Ball
+
: Depopulated Ball
Top View (See the balls through the Package)
1
A
B
C
D
E
F
G
H
J
K
L
2
3
4
5
6
7
8
9
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
V59C1512(404/804/164)QA Rev. 1.0 September 2005
3
ProMOS TECHNOLOGIES
V59C1512(404/804/164)QA
x8 package pinout (Top View) : 60ball FBGA Package
1
VDD
DQ6
VDDQ
DQ4
VDDL
2
NU/
RDQS
VSSQ
DQ1
VSSQ
VREF
CKE
NC
BA0
A10
VSS
A3
A7
VDD
A12
3
VSS
DM/
RDQS
VDDQ
DQ3
VSS
WE
BA1
A1
A5
A9
NC
A
B
C
D
E
F
G
H
J
K
L
7
VSSQ
DQS
VDDQ
DQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
8
DQS
VSSQ
DQ0
VSSQ
CK
CK
CS
A0
A4
A8
A13
VSS
VDD
9
VDDQ
DQ7
VDDQ
DQ5
VDD
ODT
Notes:
1. Pins B3 and A2 have identical capacitance as pins B7 and A8.
2. For a read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair DQS
& DQS and input masking function is disabled.
3. The function of DM or RDQS/RDQS are enabled by EMRS command.
4. VDDL and VSSDL are power and ground for the DLL. It is recommended that they are isolated on the device
from VDD, VDDQ, VSS, and VSSQ.
Ball Locations (x8)
: Populated Ball
+
: Depopulated Ball
Top View (See the balls through the Package)
1
A
B
C
D
E
F
G
H
J
K
L
2
3
4
5
6
7
8
9
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
V59C1512(404/804/164)QA Rev. 1.0 September 2005
4
ProMOS TECHNOLOGIES
V59C1512(404/804/164)QA
x16 package pinou t (Top View) : 84 ball FBGA Packa ge
1
VDD
UDQ6
VDDQ
UDQ4
VDD
LDQ6
VDDQ
LDQ4
VDDL
2
NC
VSSQ
UDQ1
VSSQ
NC
VSSQ
LDQ1
VSSQ
VREF
CKE
3
VSS
UDM
VDDQ
UDQ3
VSS
LDM
VDDQ
LDQ3
VSS
WE
BA1
A1
A5
A9
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
7
VSSQ
UDQS
VDDQ
UDQ2
VSSQ
8
UDQS
VSSQ
UDQ0
VSSQ
LDQS
VSSQ
LDQ0
VSSQ
CK
CK
CS
A0
A4
A8
NC
9
VDDQ
UDQ7
VDDQ
UDQ5
VDDQ
LDQ7
VDDQ
LDQ5
VDD
ODT
LDQS
VDDQ
LDQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
NC
BA0
A10
VDD
VSS
A3
A7
VSS
VDD
A12
Notes:
VDDL and VSSDL are power and ground for the DLL. lt is recommended that they are isolated on the device
from VDD, VDDQ, VSS, and VSSQ.
1
2
3
4
5
6
7
8
9
Ball Locations (x16)
: Populated Ball
+
: Depo pul ated Ball
A
B
C
D
E
F
Top View
(See the balls through the Package)
G
H
J
K
L
M
N
P
R
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
V59C1512(404/804/164)QA Rev. 1.0 September 2005
5
More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

V59C1512164QAJ-37 Related Products

V59C1512164QAJ-37 V59C1512164QAJ-3 V59C1512404QAJ-5 V59C1512804QAJ-5 V59C1512164QAJ-5 V59C1512804QAJ-3 V59C1512804QAJ-37 V59C1512404QAJ-37 V59C1512404QAJ-3
Description 32MX16 DDR DRAM, 0.5ns, PBGA84, GREEN, MO-207, FBGA-84 32MX16 DDR DRAM, 0.45ns, PBGA84, GREEN, MO-207, FBGA-84 128MX4 DDR DRAM, 0.6ns, PBGA60, GREEN, MO-207, FBGA-60 64MX8 DDR DRAM, 0.6ns, PBGA60, GREEN, MO-207, FBGA-60 32MX16 DDR DRAM, 0.6ns, PBGA84, GREEN, MO-207, FBGA-84 64MX8 DDR DRAM, 0.45ns, PBGA60, GREEN, MO-207, FBGA-60 64MX8 DDR DRAM, 0.5ns, PBGA60, GREEN, MO-207, FBGA-60 128MX4 DDR DRAM, 0.5ns, PBGA60, GREEN, MO-207, FBGA-60 128MX4 DDR DRAM, 0.45ns, PBGA60, GREEN, MO-207, FBGA-60
Maker ProMOS Technologies Inc ProMOS Technologies Inc ProMOS Technologies Inc ProMOS Technologies Inc ProMOS Technologies Inc ProMOS Technologies Inc ProMOS Technologies Inc ProMOS Technologies Inc ProMOS Technologies Inc
Parts packaging code DSBGA DSBGA DSBGA DSBGA DSBGA DSBGA DSBGA DSBGA DSBGA
package instruction GREEN, MO-207, FBGA-84 TFBGA, TFBGA, GREEN, MO-207, FBGA-60 TFBGA, GREEN, MO-207, FBGA-60 GREEN, MO-207, FBGA-60 TFBGA, GREEN, MO-207, FBGA-60
Contacts 84 84 60 60 84 60 60 60 60
Reach Compliance Code unknown unknown unknown unknown unknown unknown unknown unknown unknow
access mode FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST
Maximum access time 0.5 ns 0.45 ns 0.6 ns 0.6 ns 0.6 ns 0.45 ns 0.5 ns 0.5 ns 0.45 ns
Other features AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH
JESD-30 code R-PBGA-B84 R-PBGA-B84 R-PBGA-B60 R-PBGA-B60 R-PBGA-B84 R-PBGA-B60 R-PBGA-B60 R-PBGA-B60 R-PBGA-B60
length 12.5 mm 12.5 mm 12.5 mm 12.5 mm 12.5 mm 12.5 mm 12.5 mm 12.5 mm 12.5 mm
memory density 536870912 bit 536870912 bit 536870912 bit 536870912 bit 536870912 bit 536870912 bit 536870912 bit 536870912 bit 536870912 bi
Memory IC Type DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM
memory width 16 16 4 8 16 8 8 4 4
Number of functions 1 1 1 1 1 1 1 1 1
Number of ports 1 1 1 1 1 1 1 1 1
Number of terminals 84 84 60 60 84 60 60 60 60
word count 33554432 words 33554432 words 134217728 words 67108864 words 33554432 words 67108864 words 67108864 words 134217728 words 134217728 words
character code 32000000 32000000 128000000 64000000 32000000 64000000 64000000 128000000 128000000
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C
organize 32MX16 32MX16 128MX4 64MX8 32MX16 64MX8 64MX8 128MX4 128MX4
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm
Maximum supply voltage (Vsup) 1.9 V 1.9 V 1.9 V 1.9 V 1.9 V 1.9 V 1.9 V 1.9 V 1.9 V
Minimum supply voltage (Vsup) 1.7 V 1.7 V 1.7 V 1.7 V 1.7 V 1.7 V 1.7 V 1.7 V 1.7 V
Nominal supply voltage (Vsup) 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V
surface mount YES YES YES YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal form BALL BALL BALL BALL BALL BALL BALL BALL BALL
Terminal pitch 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm
Terminal location BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM
width 10 mm 10 mm 10 mm 10 mm 10 mm 10 mm 10 mm 10 mm 10 mm

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