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PALCE16V8-25JCT

Description
Flash PLD, 25ns, CMOS, PQCC20, PLASTIC, LCC-20
CategoryProgrammable logic devices    Programmable logic   
File Size263KB,13 Pages
ManufacturerCypress Semiconductor
Download Datasheet Parametric View All

PALCE16V8-25JCT Overview

Flash PLD, 25ns, CMOS, PQCC20, PLASTIC, LCC-20

PALCE16V8-25JCT Parametric

Parameter NameAttribute value
MakerCypress Semiconductor
Parts packaging codeQLCC
package instructionQCCJ,
Contacts20
Reach Compliance Codeunknown
Other features8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; POWER-UP RESET
maximum clock frequency37 MHz
JESD-30 codeS-PQCC-J20
length8.9662 mm
Dedicated input times8
Number of I/O lines8
Number of terminals20
Maximum operating temperature75 °C
Minimum operating temperature
organize8 DEDICATED INPUTS, 8 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Package shapeSQUARE
Package formCHIP CARRIER
Programmable logic typeFLASH PLD
propagation delay25 ns
Certification statusNot Qualified
Maximum seat height4.57 mm
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL EXTENDED
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
width8.9662 mm
16V8
PALCE16V8
Flash Erasable,
Reprogrammable CMOS PAL
®
Device
Features
• Active pull-up on data input pins
• Low power version (16V8L)
— 55 mA max. commercial (10, 15, 25 ns)
— 65 mA max. industrial (10, 15, 25 ns)
— 65 mA military (15 and 25 ns)
• Standard version has low power
— 90 mA max. commercial (10, 15, 25 ns)
— 115 mA max. commercial (7 ns)
— 130 mA max. military/industrial (10, 15, 25 ns)
• CMOS Flash technology for electrical erasability and
reprogrammability
• PCI compliant
• User-programmable macrocell
— Output polarity control
— Individually selectable for registered or combinato-
rial operation
• Up to 16 input terms and 8 outputs
7.5 ns com’l version
5 ns t
CO
5 ns t
S
7.5 ns t
PD
125-MHz state machine
10 ns military/industrial versions
7 ns t
CO
10 ns t
S
10 ns t
PD
62-MHz state machine
• High reliability
— Proven Flash technology
— 100% programming and functional testing
Functional Description
The Cypress PALCE16V8 is a CMOS Flash Electrical Eras-
able second-generation programmable array logic device. It is
implemented with the familiar sum-of-product (AND-OR) logic
structure and the programmable macrocell.
Logic Block Diagram (PDIP/CDIP)
GND
10
I
8
9
I
7
8
I
6
7
I
5
6
I
4
5
I
3
4
I
2
3
I
1
2
CLK/I
0
1
PROGRAMMABLE
AND ARRAY
(64 x 32)
8
8
8
8
8
8
8
8
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
11
OE/I
9
12
I/O
0
13
I/O
1
14
I/O
2
15
I/O
3
16
I/O
4
17
I/O
5
18
I/O
6
19
I/O
7
20
V
CC
16V8–1
Pin Configurations
CLK/I
0
I
1
I
2
I
3
I
4
I
5
I
6
I
7
I
8
GND
I
8
GND
OE/I
9
I/O
0
I/O
1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
OE/I
9
I
2
I
1
CLK/I
0
V
CC
I/O
7
I
3
I
4
I
5
I
6
I
7
16V8–2
DIP
Top View
PLCC/LCC
Top View
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10111213
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
16V8–3
Cypress Semiconductor Corporation
Document #: 38-03025 Rev. **
3901 North First Street
San Jose
CA 95134 • 408-943-2600
Revised September 3, 1998
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