PRELIMINARY
S29CD032G
S29CD016G
32 Mbit (1M x 32-Bit), 16 Mbit (512K x 32-Bit),
2.5 V, Burst, Dual Boot Flash
This product family has been retired and is not recommended for designs. For new and current designs, the S29CD016J and
S29CD032J supercede S29CD016G and S29CD032G respectively. This is the factory-recommended migration path. Please refer
to the S29CD-J data sheet for specifications and ordering information. Availability of this document is retained for reference and
historical purposes only.
Distinctive Characteristics
Architecture Advantages
Simultaneous Read/Write Operations
– Read data from one bank while executing erase/program
functions in other bank
– Zero latency between read and write operations
– Two bank architecture: large bank/small bank 75% / 25%
User-Defined x32 Data Bus
Dual Boot Block
– Top and bottom boot sectors in the same device
Flexible Sector Architecture
– CD032G: Eight 2K Double Word, Sixty-two 16K Double Word, and
Eight 2K Double Word sectors
– CD016G: Eight 2K Double Word, Thirty-two 16K Double Word,
and Eight 2K Double Word sectors
Secured Silicon Sector (256 Bytes)
–
Factory locked and identifiable:
16 bytes for secure, random
factory Electronic Serial Number; Also know as Electronic Marking
Manufactured on 170 nm Process Technology
Programmable Burst Interface
– Interfaces to any high performance processor
– Linear Burst Read Operation: 2, 4, and 8 double word linear burst
with or without wrap around
– Standby mode: CMOS: 60 µA max
1 million write cycles per sector typical
20 year data retention typical
VersatileI/O™ Control
– Generates data output voltages and tolerates data input voltages
as determined by the voltage on the V
IO
pin
– 1.65 V to 3.60 V compatible I/O signals
de
m
en
ec
Program Operation
– Performs synchronous and asynchronous write operations of
burst configuration register settings independently
om
Compatibility with JEDEC standards (JC42.4)
– Software compatible with single-power supply Flash
– Backward-compatible with AMD/Fujitsu Am29LV/MBM29LV and
Am29F/MBM29F flash memories
ot
R
Single Power Supply Operation
– Optimized for 2.5 to 2.75 volt read, erase, and program operations
N
Performance Characteristics
High Performance Read Access
– Initial/random access times of 48 ns (32 Mb) and 54 ns (16 Mb)
– Burst access times of 7.5 ns (32 Mb) or 9 ns (16Mb)
Ultra Low Power Consumption
– Burst Mode Read: 90 mA @ 75 MHz max
– Program/Erase: 50 mA max
General Description
The S29CD-G Flash Family is a burst mode, Dual Boot, Simultaneous Read/Write family of Flash Memory with VersatileI/O™
manufactured on 170 nm Process Technology.
The S29CD032G is a 32 Megabit, 2.6 Volt-only (2.50 V - 2.75 V) single power supply burst mode flash memory device that can be
configured for 1,048,576 double words.
Cypress Semiconductor Corporation
Document Number: 002-01299 Rev. *A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
d
Password Sector Protection
– Locks combinations of individual sectors and sector groups to
prevent program or erase operations within that sector using a
user-definable 64-bit password
Supports Common Flash Interface (CFI)
Unlock Bypass Program Command
– Reduces overall programming time when issuing multiple program
command sequences
fo
Data# Polling and Toggle Bits
– Provides a software method of detecting program or erase
operation completion
Hardware Features
Program Suspend/Resume & Erase Suspend/Resume
– Suspends program or erase operations to allow reading,
programming, or erasing in same bank
Hardware Reset (RESET#), Ready/Busy# (RY/BY#), and Write
Protect (WP#) Inputs
ACC Input
– Accelerates programming time for higher throughput during
system production
Package Options
– 80-pin PQFP
– 80-ball Fortified BGA
– Pb-free package option also available
– Known Good Die
rN
Persistent Sector Protection
– Locks combinations of individual sectors and sector groups to
prevent program or erase operations within that sector (requires
only V
CC
levels)
ew
D
Software Features
es
ig
n
PRELIMINARY
S29CD032G
S29CD016G
The S29CD016G is a 16 Megabit, 2.6 Volt-only (2.50 V - 2.75 V) single power supply burst mode flash memory device that can be
configured for 524,288 double words.
To eliminate bus contention, each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
Additional control inputs are required for synchronous burst operations: Load Burst Address Valid (ADV#), and Clock (CLK).
Each device requires only a single 2.6 Volt-only (2.50 V – 2.75 V) for both read and write functions. A 12.0-volt V
PP
is not required
for program or erase operations, although an acceleration pin is available if faster programming performance is required.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. The software command set is
compatible with the command sets of the 5 V Am29F or MBM29F and 3 V Am29LV or MBM29LV Flash families. Commands are
written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-
machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the
programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
The
Unlock Bypass
mode facilitates faster programming times by requiring only two write cycles to program data instead of four.
The
Simultaneous Read/Write architecture
provides simultaneous operation by dividing the memory space into two banks. The
device can begin programming or erasing in one bank, and then simultaneously read from the other bank, with zero latency. This
releases the system from waiting for the completion of program or erase operations. See
Simultaneous Read/Write Operations
Overview
on page 20.
The device provides a 256-byte
Secured Silicon Sector
that contains Electronic Marking Information for easy device traceability.
In addition, the device features several levels of sector protection, which can disable both the program and erase operations in
certain sectors or sector groups:
Persistent Sector Protection
is a command sector protection method that replaces the old 12 V
controlled protection method;
Password Sector Protection
is a highly sophisticated protection method that requires a password
before changes to certain sectors or sector groups are permitted;
WP# Hardware Protection
prevents program or erase in the two
outermost 8 Kbytes sectors of the larger bank.
The device defaults to the Persistent Sector Protection mode. The customer must then choose if the Standard or Password
Protection method is most desirable. The WP# Hardware Protection feature is always available, independent of the other protection
method chosen.
The
VersatileI/O™ (V
CCQ
)
feature allows the output voltage generated on the device to be determined based on the V
IO
level. This
feature allows this device to operate in the 1.8 V I/O environment, driving and receiving signals to and from other 1.8 V devices on
the same bus.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, by reading the DQ7
(Data# Polling), or DQ6 (toggle)
status bits.
After a program or erase cycle is completed, the device is ready to read array data or
accept another command.
The
sector erase architecture
allows memory sectors to be erased and reprogrammed without affecting the data contents of other
sectors. The device is fully erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations during power
transitions. The
password and software sector protection
feature disables both program and erase operations in any combination
of sectors of memory. This can be achieved in-system at V
CC
level.
The
Program/Erase Suspend/Erase Resume
feature enables the user to put erase on hold for any period of time to read data
from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation in progress and resets the internal state machine to reading array data.
The device offers two power-saving features. When addresses are stable for a specified amount of time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consumption is greatly reduced in
both these modes.
AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality,
reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim
tunnelling. The data is programmed using hot electron injection.
Document Number: 002-01299 Rev. *A
N
ot
R
ec
om
m
en
de
d
fo
rN
ew
D
es
ig
n
Page 2 of 84
PRELIMINARY
S29CD032G
S29CD016G
Contents
1.
2.
3.
4.
5.
6.
7.
7.1
Product Selector Guide
............................................... 5
Ordering Information
................................................... 6
Block Diagram..............................................................
7
Block Diagram of Simultaneous Read/Write Circuit.
8
Connection Diagram - 80-Pin PQFP
........................... 9
Physical Dimensions - PRQ080–80-Lead Plastic
Quad Flat Package.....................................................
10
Connection Diagram - 80-Ball Fortified BGA
.......... 11
Special Package Handling Instructions........................ 11
15.8 Chip Erase Command................................................... 41
15.9 Sector Erase Command................................................ 41
15.10Sector Erase and Program Suspend Command .......... 42
15.11Sector Erase and Program Suspend Operation
Mechanics..................................................................... 42
15.12Sector Erase and Program Resume Command ........... 44
15.13Configuration Register Read Command....................... 44
15.14Configuration Register Write Command....................... 44
15.15Common Flash Interface (CFI) Command ................... 44
15.16Password Program Command ..................................... 45
15.17Password Verify Command .......................................... 45
15.18Password Protection Mode Locking Bit Program
Command ..................................................................... 45
15.19Persistent Sector Protection Mode Locking Bit Program
Command ..................................................................... 45
15.20PPB Lock Bit Set Command......................................... 45
15.21DYB Write Command ................................................... 46
15.22Password Unlock Command ........................................ 46
15.23PPB Program Command .............................................. 46
15.24All PPB Erase Command ............................................. 46
15.25DYB Write..................................................................... 47
15.26PPB Lock Bit Set .......................................................... 47
15.27DYB Status ................................................................... 47
15.28PPB Status ................................................................... 47
15.29PPB Lock Bit Status ..................................................... 47
15.30Non-volatile Protection Bit Program And Erase Flow ... 47
16.
16.1
16.2
16.3
16.4
16.5
16.6
16.7
17.
18.
11.
Memory Map and Sector Protect Groups
................ 15
19
19
20
20
21
21
22
22
22
23
24
24
27
29
R
12. Device Operations
.....................................................
12.1 VersatileI/O™ (V
IO
) Control .........................................
12.2 Requirements for Reading Array Data.........................
12.3 Simultaneous Read/Write Operations Overview..........
12.4 Writing Commands/Command Sequences..................
12.5 Automatic Sleep Mode (ASM)......................................
12.6 RESET#: Hardware Reset Pin.....................................
12.7 Output Disable Mode ...................................................
12.8 Autoselect Mode ..........................................................
12.9 Asynchronous Read Operation (Non-Burst) ................
12.10Synchronous (Burst) Read Operation .........................
12.11Linear Burst Read Operations .....................................
12.12Configuration Register.................................................
12.13Initial Access Delay Configuration ...............................
de
d
ec
om
m
en
13.
13.1
13.2
13.3
13.4
13.5
13.6
Sector Protection
.......................................................
Persistent Sector Protection ........................................
Persistent Sector Protection Mode Locking Bit............
Password Protection Mode ..........................................
Password and Password Mode Locking Bit.................
Write Protect (WP#) .....................................................
Secured Silicon OTP Sector and Simultaneous
Operation .....................................................................
13.7 Persistent Protection Bit Lock ......................................
13.8 Hardware Data Protection............................................
29
29
31
31
32
32
32
32
33
ot
N
14.
15.
15.1
15.2
15.3
15.4
15.5
15.6
15.7
Common Flash Memory Interface (CFI)
................... 34
Command Definitions................................................
Reading Array Data in Non-burst Mode.......................
Reading Array Data in Burst Mode ..............................
Read/Reset Command ................................................
Autoselect Command...................................................
Program Command Sequence ....................................
Accelerated Program Command..................................
Unlock Bypass Command Sequence ..........................
37
37
37
38
38
38
39
39
Document Number: 002-01299 Rev. *A
fo
20.
21.
22.
23.
24.
24.1
24.2
24.3
24.4
24.5
24.6
25.
19. DC Characteristics......................................................
57
19.1 CMOS Compatible ........................................................ 57
19.2 Zero Power Flash.......................................................... 58
Test Conditions
........................................................... 59
Test Specifications
..................................................... 59
Key to Switching Waveforms.....................................
59
Switching Waveforms.................................................
59
AC Characteristics......................................................
60
VCC and VIO Power-up................................................ 60
Asynchronous Read Operations ................................... 60
Burst Mode Read for 32 Mb & 16 Mb ........................... 62
Hardware Reset (RESET#)........................................... 64
Erase/Program Operations ........................................... 66
Alternate CE# Controlled Erase/Program Operations .. 70
Erase and Programming Performance
..................... 71
Page 3 of 84
rN
Write Operation Status
............................................... 51
DQ7: Data# Polling ....................................................... 51
RY/BY#: Ready/Busy#.................................................. 51
DQ6: Toggle Bit I .......................................................... 53
DQ2: Toggle Bit II ......................................................... 53
Reading Toggle Bits DQ6/DQ2..................................... 53
DQ5: Exceeded Timing Limits ...................................... 54
DQ3: Sector Erase Timer.............................................. 54
Absolute Maximum Ratings.......................................
55
Operating Ranges
....................................................... 56
ew
10. Logic Symbols
........................................................... 13
10.1 S29CD032G................................................................. 13
10.2 S29CD016G................................................................. 14
D
es
9.
Pin Configuration.......................................................
13
ig
n
8.
Physical Dimensions - LAA080–80-ball Fortified Ball
Grid Array (13 x 11 mm)
..................................................... 12
PRELIMINARY
S29CD032G
S29CD016G
26.
27.
Latchup Characteristics
............................................ 72
PQFP and Fortified BGA Pin Capacitance...............
72
28. Revision Summary.....................................................
73
28.1 S29CD016G Revision History...................................... 73
28.2 Family Data Sheet Revision History ............................ 76
Document Number: 002-01299 Rev. *A
N
ot
R
ec
om
m
en
de
d
fo
rN
ew
D
es
ig
n
Page 4 of 84
PRELIMINARY
S29CD032G
S29CD016G
1.
Product Selector Guide
Part Number
S29CD-G Flash Family
(S29CD032G, S29CD016G)
Synchronous/Burst or Asynchronous
0R
(75 MHz)
(32 Mb Only)
48
7.5 FBGA
75
3
52
0P
(66 MHz)
54
9 FBGA/
9.5 PQFP
66
3
58
20
0M
(56 MHz)
64
10 FBGA/
10 PQFP
56
3
69
0J
(40 MHz)
67
17
40
2
V
CC
= 2.5 – 2.75 V
V
IO
= 1.65 – 2.75 V
Standard Voltage Range:
Speed Option (Clock Rate)
Max Initial/Asynchronous Access Time, ns (t
ACC
)
Max Burst Access Delay (ns)
Max Clock Rate (MHz)
Min Initial Clock Delay (clock cycles)
Max CE# Access, ns (t
CE
)
Max OE# Access, ns (t
OE
)
Document Number: 002-01299 Rev. *A
N
ot
R
ec
om
m
en
de
d
fo
rN
ew
D
es
ig
n
71
28
Page 5 of 84
京公网安备 11010802033920号
EEWORLD
