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Datasheet> All Categories > logic> logic> ICS8745AMI-21T
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ICS8745AMI-21T

Description
PLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2.30 MM HEIGHT, SOIC-20
Categorylogic    logic   
File Size154KB，13 Pages
ManufacturerIDT (Integrated Device Technology)
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ICS8745AMI-21T Overview

PLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2.30 MM HEIGHT, SOIC-20

ICS8745AMI-21T Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeSOIC
package instructionSOP,
Contacts20
Reach Compliance Codecompliant
Input adjustmentDIFFERENTIAL
JESD-30 codeR-PDSO-G20
JESD-609 codee0
length12.8 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Number of functions1
Number of inverted outputs
Number of terminals20
Actual output times1
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)225
propagation delay (tpd)5.7 ns
Certification statusNot Qualified
Same Edge Skew-Max（tskwd）0.03 ns
Maximum seat height2.65 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width7.5 mm
minfmax31.25 MHz

ICS8745AMI-21T Preview

Integrated
Circuit
Systems, Inc.
ICS8745I-21
D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
F
EATURES
•
1 differential LVDS output pair designed to meet
or exceed the requirements of ANSI TIA/EIA-644
1 differential feedback output pair
•
Differential CLK, nCLK input pair
•
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Output frequency range: 31.25MHz to 700MHz
•
Input frequency range: 31.25MHz to 700MHz
•
VCO range: 250MHz to 700MHz
•
External feedback for “zero delay” clock regeneration
with configurable frequencies
•
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
•
Cycle-to-cycle jitter: 25ps (maximum)
•
Static phase offset: 50ps ± 200ps
•
3.3V supply voltage
•
-40°C to 85°C ambient operating temperature
G
ENERAL
D
ESCRIPTION
The ICS8745I-21 is a highly versatile 1:1 LVDS
clock generator and a member of the
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS8745I-21 has a fully
integrated PLL and can be configured as zero
delay buffer, multiplier or divider, and has an output fre-
quency range of 31.25MHz to 700MHz. The Reference
Divider, Feedback Divider and Output Divider are each
programmable, thereby allowing for the following output-
to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8.
The external feedback allows the device to achieve “zero
delay” between the input clock and the output clocks. The
PLL_SEL pin can be used to bypass the PLL for system
test and debug purposes. In bypass mode, the reference
clock is routed around the PLL and into the internal
output dividers.
,&6
B
LOCK
D
IAGRAM
PLL_SEL
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
P
IN
A
SSIGNMENT
0
1
Q
nQ
QFB
nQFB
CLK
nCLK
MR
nFB_IN
FB_IN
SEL2
V
DDO
nQFB
QFB
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SEL1
SEL0
V
DD
PLL_SEL
V
DDA
SEL3
GND
Q
nQ
V
DDO
CLK
nCLK
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
FB_IN
nFB_IN
ICS8745I-21
20-Lead, 300-MIL SOIC
7.5mm x 12.8mm x 2.3mm body package
M Package
Top View
SEL0
SEL1
SEL2
SEL3
MR
8745AMI-21
www.icst.com/products/hiperclocks.html
1
REV. A JANUARY 31, 2003
Integrated
Circuit
Systems, Inc.
ICS8745I-21
D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
Type
Description
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6
7, 11
8, 9
10, 14
12, 13
15
16
17
18
19
20
Name
CLK
nCLK
MR
nFB_IN
FB_IN
SEL2
V
DDO
GND
nQ, Q
SEL3
V
DDA
PLL_SEL
V
DD
SEL0
SEL1
Input
Input
Input
Input
Input
Input
Power
Power
Output
Input
Power
Input
Power
Input
Input
Pullup
Pulldown Non-inver ting differential clock input.
Inver ting differential clock input.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx, QFB to go low and the inver ted outputs nQx,
Pulldown
nQFB to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS / LVTTL interface levels.
Pullup Feedback input to phase detector for regenerating clocks with "zero delay".
Pulldown Feedback input to phase detector for regenerating clocks with "zero delay".
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Output supply pins.
Differential feedback outputs. LVDS interface levels.
Power supply ground.
Differential clock outputs. LVDS interface levels.
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Analog supply pin.
Selects between the PLL and reference clock as the input to the dividers.
When HIGH, selects PLL. When LOW, selects the reference clock.
LVCMOS / LVTTL interface levels.
Core supply pin.
Pullup
nQFB, QFB Output
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
51
51
Test Conditions
Minimum
Typical
Maximum
4
Units
pF
KΩ
KΩ
8745AMI-21
www.icst.com/products/hiperclocks.html
2
REV. A JANUARY 31, 2003
Integrated
Circuit
Systems, Inc.
ICS8745I-21
D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
Outputs
PLL_SEL = 1
PLL Enable Mode
Q, QFB; nQ0, nQFB
÷1
÷1
÷1
÷1
÷2
÷2
÷2
÷4
÷4
÷8
x2
x2
x2
x4
x4
x8
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reference Frequency Range (MHz)*
250 - 700
125 - 350
62.5 - 175
31.25 - 87.5
250 - 700
125 - 350
62.5 - 175
250 -700
125 - 350
250 - 700
125 - 350
62.5 - 175
31.25 - 87.5
62.5 - 175
31.25 - 87.5
31.25 - 87.5
*NOTE: VCO frequency range for all configurations above is 250 to 700MHz.
T
ABLE
3B. PLL B
YPASS
F
UNCTION
T
ABLE
Inputs
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
8745AMI-21
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Outputs
PLL_SEL = 0
PLL Bypass Mode
Q, QFB; nQ0, nQFB
÷4
÷4
÷4
÷8
÷8
÷8
÷ 16
÷ 16
÷ 32
÷ 64
÷2
÷2
÷4
÷1
÷2
÷1
REV. A JANUARY 31, 2003
www.icst.com/products/hiperclocks.html
3
Integrated
Circuit
Systems, Inc.
ICS8745I-21
D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
85
15
20
Units
V
V
V
mA
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
MR, SEL0, SEL1,
SEL2, SEL3
PLL_SEL
MR, SEL0, SEL1,
SEL2, SEL3
I
IL
Input Low Current
PLL_SEL
V
DD
= 3.465V, V
IN
= 0V
-150
µA
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
I
IH
I
IL
V
PP
V
CMR
Input High Current
Input Low Current
CLK, FB_IN
nCLK, nFB_IN
CLK, FB_IN
nCLK, nFB_IN
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
0.15
GND + 0.5
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is V
DD
+ 0.3V.
8745AMI-21
www.icst.com/products/hiperclocks.html
4
REV. A JANUARY 31, 2003
Integrated
Circuit
Systems, Inc.
ICS8745I-21
D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
Test Conditions
Minimum
230
1.0
-3.5
CLK = V
DD
, Q = 0V or
CLK = 0V, nQ = 0V
V
OUT
= 0V or 3.465V,
V
DD
= 0V
-20
-3.5
±1
Typical
350
Maximum
460
50
1.5
50
-4.6
-4.6
+20
Units
mV
mV
V
mV
mA
mA
µA
T
ABLE
4D. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OD
∆
V
OD
V
OS
∆
V
OS
I
OSD
I
OS
I
OFF
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Differential Output Shor t Circuit Current
Output Shor t Circuit Current
Power Off Leakage
T
ABLE
5. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
IN
Parameter
Input Frequency
CLK, nCLK
Test Conditions
PLL_SEL = 1
PLL_SEL = 0
Minimum
31.25
Typical
Maximum
700
700
Units
MHz
MHz
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 4, 5
Static Phase Offset; NOTE 2, 5, 6
Cycle-to-Cycle Jitter; NOTE 5, 6
Phase Jitter; NOTE 3, 5
Output Pulse Width
PLL Lock Time
Output Rise/Fall Time; NOTE 7
f
≤
155.5MHz
150
t
PERIOD
/2 - 85
t
PERIOD
/2
PLL_SEL = 0V, f
≤
700MHz
PLL_SEL = 0V
PLL_SEL = 3.3V
-150
50
4.1
4.9
Test Conditions
Minimum
Typical
Maximum
700
5.7
30
250
25
±65
t
PERIOD
/2 + 85
1
550
45 0
Units
MHz
ns
ps
ps
ps
ps
ps
ms
ps
ps
t
sk(o)
t
(Ø)
t
jit(cc)
t
jit(
θ)
t
PW
t
L
t
R
/ t
F
f > 155.5MHz
50
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback
input signal across all conditions, when the PLL is locked and the input reference frequency is stable.
NOTE 3: Phase jitter is dependent on the input source used.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Characterized at VCO frequency of 622MHz.
NOTE 7: Measured from the 20% to 80% points. Guaranteed by characterization. Not production tested.
8745AMI-21
www.icst.com/products/hiperclocks.html
5
REV. A JANUARY 31, 2003
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ICS8745AMI-21T Related Products

ICS8745AMI-21T ICS8745AMI-21LFT ICS8745AMI-21 ICS8745AMI-21LF
Description PLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2.30 MM HEIGHT, SOIC-20 PLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2.30 MM HEIGHT, SOIC-20 PLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2.30 MM HEIGHT, SOIC-20 PLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2.30 MM HEIGHT, SOIC-20
Is it lead-free? Contains lead Lead free Contains lead Lead free
Is it Rohs certified? incompatible conform to incompatible conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code SOIC SOIC SOIC SOIC
package instruction SOP, SOP, SOP, SOP,
Contacts 20 20 20 20
Reach Compliance Code compliant compliant compliant compliant
Input adjustment DIFFERENTIAL DIFFERENTIAL DIFFERENTIAL DIFFERENTIAL
JESD-30 code R-PDSO-G20 R-PDSO-G20 R-PDSO-G20 R-PDSO-G20
JESD-609 code e0 e3 e0 e3
length 12.8 mm 12.8 mm 12.8 mm 12.8 mm
Logic integrated circuit type PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER
Number of functions 1 1 1 1
Number of terminals 20 20 20 20
Actual output times 1 1 1 1
Maximum operating temperature 85 °C 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SOP SOP SOP SOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE
Peak Reflow Temperature (Celsius) 225 260 225 260
propagation delay (tpd) 5.7 ns 5.7 ns 5.7 ns 5.7 ns
Certification status Not Qualified Not Qualified Not Qualified Not Qualified
Same Edge Skew-Max（tskwd） 0.03 ns 0.03 ns 0.03 ns 0.03 ns
Maximum seat height 2.65 mm 2.65 mm 2.65 mm 2.65 mm
Maximum supply voltage (Vsup) 3.465 V 3.465 V 3.465 V 3.465 V
Minimum supply voltage (Vsup) 3.135 V 3.135 V 3.135 V 3.135 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V
surface mount YES YES YES YES
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface Tin/Lead (Sn/Pb) Matte Tin (Sn) Tin/Lead (Sn/Pb) Matte Tin (Sn)
Terminal form GULL WING GULL WING GULL WING GULL WING
Terminal pitch 1.27 mm 1.27 mm 1.27 mm 1.27 mm
Terminal location DUAL DUAL DUAL DUAL
Maximum time at peak reflow temperature 30 30 30 30
width 7.5 mm 7.5 mm 7.5 mm 7.5 mm
minfmax 31.25 MHz 31.25 MHz 31.25 MHz 31.25 MHz

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