Preliminary
GS8170DW18/36/72C-333/300/250
209-Bump BGA
Commercial Temp
Industrial Temp
18Mb
Σ1x1
Double Late Write
SigmaRAM™ SRAM
250 MHz–333 MHz
1.8 V V
DD
1.8 V and 1.5 V I/O
Features
• Double Late Write mode
• JEDEC-standard SigmaRAM
™
pinout and package
• 1.8 V +150/–100 mV core power supply
• 1.5 V or 1.8 V I/O supply
• Dual Cycle Deselect
• Synchronous Burst operation
• Fully coherent read and write pipelines
• Echo Clock outputs track data output drivers
• ZQ mode pin for user-selectable output drive strength
• Byte write operation (9-bit bytes)
• 2 user-programmable chip enable inputs for easy depth
expansion
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
- 333
3.0 ns
1.6 ns
Bottom View
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
Pipeline mode
tKHKH
tKHQV
SigmaRAM Family Overview
GS8170DW18/36/72 SigmaRAMs (ΣRAM
™)
are built in
compliance with the
ΣRAM
pinout standard for synchronous
SRAMs. They are 18,874,368-bit (18Mb) SRAMs. These are
the first in a family of wide, very low voltage CMOS I/O
SRAMs designed to operate at the speeds needed to implement
economical high performance networking systems.
GSI's
ΣRAMs
are offered in a number of configurations that
emulate other synchronous SRAMs, such as Burst RAMs,
NBT, Late Write, or Double Data Rate (DDR) SRAMs. The
logical differences between the protocols employed by these
RAMs hinge mainly on various combinations of address
bursting, output data registering and write cueing. The
ΣRAM
family standard allows a user to implement the interface
protocol best suited to the task at hand.
Functional Description
Because
ΣRAMs
are synchronous devices, address, data
inputs, and read/write control inputs are captured on the rising
edge of the input clock. Write cycles are internally self-timed
and initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing.
The GS8170DW18/36/72C is configured to read in Pipeline
mode. In Pipeline mode, single data rate
ΣRAMs
incorporate a
rising-edge-triggered output register. For read cycles, a
pipelined SRAM’s output data is staged at the input of an edge-
triggered output register during the access cycle and then
released to the output drivers at the next rising edge of clock.
GS8170DW18/36/72C
ΣRAMs
are implemented with GSI's
high performance CMOS technology and are packaged in a
209-bump BGA.
Rev: 1.00d 6/2002
1/36
© 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8170DW18/36/72C-333/300/250
Pin Description Table
Pin Location
A3, A5, A7, A9, B7, U4,
U6, U8, V3, V4, V5, V6,
V7, V8, V9, W5, W6, W7
C7
B5
A6
B3, C9
B8, C4
B4, B9, C3, C8
K3
K1, K11
K2, K10
E2, F1, F2, G1, G2, H1,
H2, J1, J2, L10, L11,
M10, M11, N10, N11,
P10, P11, R10
A10, A11, B10, B11,
C10, C11, D10, D11,
E11, R1, T1, T2, U1, U2,
V1, V2, W1, W2
A1, A2, B1, B2, C1, C2,
D1, D2, E1, E10, F10,
F11, G10, G11, H10,
H11, J10, J11, L1, L2,
M1, M2, N1, N2, P1, P2,
R2, R11, T10, T11, U10,
U11, V10, V11, W10,
W11
C6
A4, A8
G6, H6
W9
W4
W8
W3
J6, L6, N6
D6, K6, M6, P6, T6
Rev: 1.00d 6/2002
Symbol
A
A
A
ADV
Bx
Bx
Bx
CK
CQ
CQ
DQ
Description
Address
Address
Address
Advance
Byte Write Enable
Byte Write Enable
Byte Write Enable
Clock
Echo Clock
Echo Clock
Data I/O
Type
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Input/Output
Comments
—
x18 version only
x18 and x36 versions
Active High
Active Low (all versions)
Active Low (x36 and x72 versions)
Active Low (x72 version only)
Active High
Active High
Active Low
x18, x36, and x72 versions
DQ
Data I/O
Input/Output
x36 and x72 versions
DQ
Data I/O
Input/Output
x72 version only
E1
E2 & E3
EP2 & EP3
TCK
TDI
TDO
TMS
MCH
MCL
Chip Enable
Chip Enable
Chip Enable Program Pin
Test Clock
Test Data In
Test Data Out
Test Mode Select
Must Connect High
Must Connect Low
5/36
Input
Input
Input
Input
Input
Output
Input
Input
Input
Active Low
Programmable Active High or Low
—
Active High
—
—
—
Active High
Active Low
© 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
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