80-0208-B datasheet, PDF - EEWORLD Datasheet

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80-0208-B: DescriptionSpeech And Music Processor; File Size280KB，13 Pages; ManufacturerETC1

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80-0208-B Overview

Speech And Music Processor

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SC-604

Speech And Music Processor

Data sheet

Features

Advanced, Integrated Speech Synthesizer for

High-Quality Sound

Operates up to 12.32 MHz (Performs up to 12

MIPS)

Slave Mode Enables Hours of Speech Using an

External Processor and Memory

Master Mode Allows 6.8 Minutes of Speech

Onboard

Supports High-Quality Synthesis Algorithms

such as MX, CX, Simple CX, LX, ADPCM, and

Polyphonic Music

Simultaneous Speech Plus Music Capabilities

Very Low-Power Operation, Ideal for Hand-Held

Devices

Low-Voltage Operation, Sustainable by Three

(3) Batteries

Reduced Power Standby Modes, Less Than 10

µA

in Deep-Sleep Mode

16 General-Purpose I/O Pins (in Master Mode)

or 4 General-Purpose I/O Pins (in Slave Mode)

Resistor-Trimmed Oscillator or 32.768-kHz

Crystal Reference Oscillator

Slave Interface Logic Contains 64K Bytes-

Words Onboard ROM (2K Words Reserved)

640-Word RAM

Direct Speaker Drive, 32

Ω

(PDM)

One-Bit Comparator With Edge Detection

Interrupt Service

Serial Scan Port for In-Circuit Emulation,

Monitor, and Test

Available in Die Form or 64-Pin LQFP Package

Description

The SC-604 is a low-cost, mixed-signal

processor that combines a speech synthesizer

with a dedicated slave interface logic, general-

purpose I/O, onboard ROM, and direct speaker-

drive in a single package. The computational

unit uses a powerful new DSP that gives the SC-

604 unprecedented speed and computational

flexibility compared with previous devices of its

type. The SC-604 supports a variety of speech

and audio coding algorithms, providing a range

of options with respect to speech duration and

sound quality.

SC-691 Block Diagram

16-Bit

Microprocessor

10-Bit

DAC

640-words

RAM

TIMER 1

TIMER 2

PLLM

SLAVE LOGIC

64K-Bytes ROM

COMPARATOR

The device consists of a micro-DSP core,

embedded program and data memory, and a self-contained clock generation system. General-purpose

periphery is comprised of 16 bits of partially configurable I/O.

The core processor is a general-purpose 16-bit microcontroller with DSP capability. The basic core block

includes a computational unit (CU), data address unit, program address unit, two timers, eight-level interrupt

processor, and several system and control registers. The core processor gives the SC-604break-point capability

in emulation.

The processor is a Harvard type for efficient DSP algorithm execution, separating program and data memory

blocks to permit simultaneous access. The ROM has a protection scheme to prevent third-party pirating. It is

configured in 32K 17-bit words.

The total ROM space is divided into two areas:

1) The lower 2K words are reserved by Sensory, Inc. for a built-in self-test

2) The upper 30K is for user program and data space.

P/N 80-0208-B

Data Sheet

SC-604

Functional Description

The SC-604 is a member of the SC-6x family, which is based on the SC-614 core. For specific details about the

core operations, instruction sets, register definitions, port configuration, etc., consult the SC-614 User’s Guide

(80-0212).

The SC-604 can be used as a slave synthesizer in slave mode or can operate stand-alone in master mode. The

slave mode activates logic circuitry internal to the device that gives the device a dedicated slave interface. The

slave or master mode is controlled by the bit 0 of the Port G (PG0). By default the device initially starts in slave

mode. To change to master mode write a 0x01 to G port 0 (0x2C). To change back to slave mode write a 0x00

to port G bit 0 (0x2C).

Master Mode

In master mode, the slave logic circuitry is disabled and SC-604has 16 general-purpose I/Os. These 16

input/output pins are organized as 2-byte-wide ports (C and D), initialized as inputs. Each of the pins can be

configured as a totem-pole output or as a high-impedance input by setting or clearing the appropriate bit in the

appropriate control register (0x14, 0x1C). When configured as an output, the data driven by the output pin can

be controlled by setting or clearing the appropriate bit in the appropriate data register (0x10, 0x18). Whether

configured as input or as output, reading the data port reads the actual state of the pin.

External interrupts can be caused by transitions on pins PD2, PD3, PD4, and PD5 in the master mode. These

interrupts are supported whether the pins are programmed as inputs or outputs.

Slave Mode

In slave mode, the slave logic circuitry is enabled allowing the device to have a dedicated slave interface. In this

mode, only four pins of port D (PD4–PD7) are available as general-purpose I/O while the remaining pins (PD0–

PD3) are redefined as INRDY, OUTRDY, STROBE and R/W. These pins are used to operate the slave

interface. The SC-604controls the INRDY and OUTRDY pins to let the external microcontroller know when the

slave is ready to accept or transmit data. The external microcontroller controls the R/W and STROBE pins of

SC-604to sequence the read/write data flow. Each read or write sequence generates an interrupt that needs to

be serviced by an interrupt service routine. These interrupt service routines need to be written by the code

developer. The INT3 interrupt service routine indicates that the host has completed the write sequence, and the

slave should read the data from port A. The INT4 interrupt service routine indicates the host has completed the

read sequence. An interrupt is not generated when a read/write is done on port G bit 0 (PG0).

The slave interface consists of:

8-bit bidirectional data bus (PC0–PC7)

2 status outputs: INRDY/PD0, and OUTRDY/PD1

2 control inputs: STROBE/PD2, and R/W/PD3

4 general-purpose I/Os (PD4–PD7)

Port C is used as an 8-bit bidirectional data bus. When data is to be sent to the host, it needs to be written to

port C data register (0x10). When data is read from the host, it needs to be read from port A data register

(0x00). Port A pins are not physically brought outside the device but are internally connected with the pins of

port C.

System Initialization Sequence In The Slave Mode

Initialize the host processor first.

The host must hold the slave RESET pin low until the slave STROBE pin can be held high by the host

throughout the slave initialization process.

The INRDY and OUTRDY pins are set high by the slave on the rising edge of the slave RESET pin.

Slave Mode Software Initialization

Write 0x00 to port A (0x00), port C (0x10), port D (0x18) data registers.

Configure the port C (PC0–PC7), port D0, and port D1 as output ports. (Write 0xFF to port C (0x14) and

0x03 to port D (0x1C) control registers)

P/N 80-0208-B

SC-604

Data sheet

Configure port A (PA0–PA7), PORT D2, and port D3 as input ports (default at reset). Write 0x00 to port A

(0x04) and 0x03 to port D (0x1C) control registers.

After the slave completes its initialization, the slave needs to inform the host that it is ready to read or write

data.

Note:

the default mode for the MSP50C604 is the slave mode. The MSP50C604 can be set to master mode by

writing a 1 to port G bit 0. This is an internal bit that is not available on the MSP50C604 external pins.

Note:

the initialization sequence given previously is a specific requirement for setting up the MSP50C604 in

slave mode. For the basic initialization requirements of the device, please refer to the MSP50C614 user’s guide

(SPSU014).

Write To Slave In The Slave Mode

The slave indicates it is ready to receive data from the host by dropping INRDY low. This is done by writing

low-high-low to port D (0x18) bit 0 (PD0).

On the falling edge of the internal PD0 pulse, INRDY toggles low, notifying the host that the slave is ready to

receive data.

The host writes data to the slave by setting R/W low and then pulsing the STROBE high-low-high.

The slave latches the data on the rising edge of the STROBE pulse and sets INRDY high.

An INT3 interrupt is generated as INRDY goes high completing the write cycle.

The latched data is read by the slave through port A (0x00) data register.

Read From Slave In The Slave Mode

When the slave has data for the host, it places the data in port C (0x10).

The slave then indicates that the data is ready by dropping OUTRDY low. This is done by writing low-high-

low to port D (0x18) bit 1 (PD1).

On the falling edge of the internal PD1 pulse, OUTRDY toggles low notifying the host that the slave is ready

to send data.

The host responds by setting R/W high and then pulsing STROBE high-low-high.

The host should latch the data before raising STROBE high.

This informs the slave that the data has been written to the host. The OUTRDY is pulled high by the slave at

the rising edge of STROBE.

An INT4 interrupt is generated as OUTRDY goes high completing the read cycle.

P/N 80-0208-B

80-0208-B Related Products

	80-0208-B	SC-604	SC604-R	SC604-RL1
Description	Speech And Music Processor	Speech And Music Processor	Speech And Music Processor	Speech And Music Processor

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