ZPSD412A2-70J datasheet, PDF - EEWORLD Datasheet

ZPSD412A2-70J: DescriptionParallel I/O Port, 40 I/O, CMOS, PQCC68,; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，108 Pages; ManufacturerWaferscale Integration Inc.

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ZPSD412A2-70J Overview

Parallel I/O Port, 40 I/O, CMOS, PQCC68,

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Waferscale Integration Inc.
Reach Compliance Code	unknown
Maximum access time	7e-8 ns
Other features	GENERAL PURPOSE ZPLD
maximum clock frequency	50 MHz
External data bus width	8
JESD-30 code	S-PQCC-J68
JESD-609 code	e0
Number of I/O lines	40
Number of ports	5
Number of terminals	68
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC68,1.0SQ
Package shape	SQUARE
Package form	CHIP CARRIER
power supply	5 V
Certification status	Not Qualified
ROM size (bits)	512 Bits
Maximum standby current	0.00002 A
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
UV erasable	N
uPs/uCs/peripheral integrated circuit type	PARALLEL IO PORT, GENERAL PURPOSE

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