DPS128C32BV3-45M datasheet, PDF

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DPS128C32BV3-45M: DescriptionSRAM Module, 128KX32, 45ns, CMOS, CPGA66, 1.090 X 1.090 INCH, 0.300 INCH HEIGHT, VERSA STACK, CERAMIC, PGA-66; Categorystorage storage; File Size760KB，7 Pages; ManufacturerTwilight Technology Inc.

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DPS128C32BV3-45M Overview

SRAM Module, 128KX32, 45ns, CMOS, CPGA66, 1.090 X 1.090 INCH, 0.300 INCH HEIGHT, VERSA STACK, CERAMIC, PGA-66

DPS128C32BV3-45M Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Twilight Technology Inc.
Parts packaging code	PGA
package instruction	PGA,
Contacts	66
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
Maximum access time	45 ns
Other features	CONFIGURABLE AS 512K X 8
Spare memory width	16
JESD-30 code	S-CPGA-P66
memory density	4194304 bit
Memory IC Type	SRAM MODULE
memory width	32
Number of functions	1
Number of terminals	66
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	128KX32
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Package shape	SQUARE
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	7.62 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED

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4 Megabit High Speed CMOS SRAM

DPS128C32BV3

DESCRIPTION:

The DPS128C32BV3 ‘’VERSA-STACK’’ module is a

revolutionary new high speed memory subsystem using

Dense-Pac Microsystems’ ceramic Stackable Leadless Chip

Carriers (SLCC) mounted on a co-fired ceramic substrate.

It offers 4 Megabits of SRAM in a package envelope of

1.090 x 1.090 x 0.300 inches.

The DPS128C32BV3 contains four individual 128K x 8

SRAMs, packaged in their own hermetically sealed SLCCs

making the module suitable for commercial, industrial and

military applications.

By using SLCCs, the ‘’Versa-Stack’’ family of modules offers

a higher board density of memory than available with

conventional through-hole, surface mount, module, or

hybrid techniques.

FEATURES:

•

Organizations Available:

128K x 32, 256K x 16, or

512K x 8

•

Access Times:

20, 25, 30, 35, 45ns

•

Fully Static Operation

- No clock or refresh required

•

Single +5V Power Supply,

±10%

Tolerance

•

TTL Compatible

•

Common Data Inputs

and Outputs

•

Low Data Retention Voltage:

2.0V min.

•

66-Pin PGA ‘’VERSA-STACK’’

Package

Commercial only.

FUNCTIONAL BLOCK DIAGRAM

PIN-OUT DIAGRAM

PIN NAMES

A0 - A16

I/O0 - I/O31

CE0 - CE3

WE0 - WE3

N.C.

Address Inputs

Data Input/Output

Chip Enables

Write Enables

Output Enable

Power (+5V)

Ground

No Connect

30A044-28

REV. F

This document contains information on a product that is currently released

to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right

to change products or specifications herein without prior notice.

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