Data Sheet
MARCH 1999
Revision 3.1
LXT901/907
Universal 10BASE-T and AUI Transceivers
General Description
The LXT901 and LXT907 Universal 10BASE-T and AUI
Transceivers are designed for IEEE 802.3 physical layer
applications. They provide all the active circuitry to
interface most standard 802.3 controllers to either the
10BASE-T media or Attachment Unit Interface (AUI). In
addition to standard 10 Mbps Ethernet, they also support
full-duplex operation at 20 Mbps.
The LXT901 and LXT907 are identical except for the
function of one pin. The LXT901 offers selectable
termination impedance to allow the use of either shielded
or unshielded twisted-pair cable. The LXT907 offers a
signal quality error (SQE) disable function.
Common LXT901 and LXT907 functions include
Manchester encoding/decoding, receiver squelch and
transmit pulse shaping, jabber, link testing and reversed
polarity detection/correction. Integrated filters simplify the
design work required for FCC-compliant EMI
performance.
Features
Functional Features
• Integrated Manchester Encoder/Decoder
• 10BASE-T Transceiver
• AUI Transceiver
• Full-Duplex Capable (20 Mbps)
Convenience Features
• Automatic/Manual AUI/RJ45 Selection
• Automatic Polarity Correction
• SQE Disable function (LXT907
only)
• Programmable Impedance Driver (LXT901
only)
• Power Down Mode and four loopback modes
• LXT901 available in 64-pin LQFP and 44-pin PLCC
• LXT907 available in 44-pin PLCC
Diagnostic Features
• Four LED Drivers
• AUI/RJ45 Loopback
• Remote Signaling of Link Down and Jabber conditions
Applications
• 10BASE-T hub and switching products
• Computer/Workstation 10BASE-T LAN adapters
LXT901/907 Block Diagram
MD0
AUTOSEL
PAUI
LBK
LI
MODE SELECT LOGIC
Controller Compatibility
Port Select
Loopback
Link test
MD1
Select:
PLS Only
or
PLS / MAU
TWISTED PAIR
INTERFACE
PULSE SHAPER
AND FILTER
DO
COLLISION/
POLARITY
DETECT
CORRECT
RC
RX
SLICER
RC
CMOS
TX
AMP
*STP
*(LXT901 only )
TPOPB
TPOPA
TPONA
TPONB
TCLK
CLKI
CLKO
TEN
TXD
XTAL
OSC
MANCHESTER
ENCODER
WATCHDOG
TIMER
TPIP
TPIN
RLD
RJAB
RCMPT
CD
LEDL
RXD
RCLK
MANCHESTER
DECODER
REMOTE SIGNALING
SQUELCH / LINK
DETECT
DROP CABLE
INTERFACE
ECL
TX
AMP
+
-
LPBK
DOP
DON
DI
RX
SLICER
DIP
DIN
CI
COLLISION LOGIC
COL
COLLISION
RECEIVER
CIP
CIN
LEDR LEDT/PDN
*DSQE
LEDC/FDE
NTH JAB
*(LXT907 only)
PLR
Refer to www.level1.com for most current information.
)
LXT901/907 Universal 10BASE-T and AUI Transceivers
LXT901/907
TABLE OF CONTENTS
PIN ASSIGNMENTS AND SIGNAL DESCRIPTIONS ......................................................3
FUNCTIONAL DESCRIPTION ..........................................................................................7
Controller Compatibility Modes .......................................................................................... 7
Transmit Function .............................................................................................................. 8
Jabber Control Function ............................................................................................. 8
SQE Function ............................................................................................................. 9
Receive Function ............................................................................................................... 9
Polarity Reverse Function .......................................................................................... 9
Collision Detection Function..................................................................................... 10
Loopback Function.......................................................................................................... 10
Link Integrity Test Function ...............................................................................................11
Remote Signaling............................................................................................................. 12
APPLICATION INFORMATION ......................................................................................13
Twisted-Pair Impedance Matching ................................................................................... 13
Crystal and Magnetics Information................................................................................... 13
Auto Port Select with External Loopback Control ............................................................ 14
Full - Duplex Support ....................................................................................................... 16
Dual Network Support - 10BASE-T and Token Ring........................................................ 17
Manual Port Select & Link Test Function ......................................................................... 18
Three Media Application .................................................................................................. 20
AUI Encoder/Decoder Only.............................................................................................. 21
Shielded Twisted-Pair Only .............................................................................................. 22
TEST SPECIFICATIONS.................................................................................................23
Absolute Maximum Ratings ............................................................................................. 23
Recommended Operating Conditions .............................................................................. 23
I/O Electrical Characteristics ............................................................................................ 24
AUI Electrical Characteristics........................................................................................... 24
Twisted-Pair Electrical Characteristics ............................................................................. 25
Switching Characteristics ................................................................................................. 25
RCLK/Start-of-Frame Timing ........................................................................................... 26
RCLK/End-of-Frame Timing............................................................................................. 26
Transmit Timing................................................................................................................ 27
Collision, COL/CI Output and Loopback Timing .............................................................. 27
Mode 1 Timing Diagrams ................................................................................................. 28
Mode 2 Timing Diagrams ................................................................................................. 30
Mode 3 Timing Diagrams ................................................................................................. 32
Mode 4 Timing Diagrams ................................................................................................. 36
MECHANICAL SPECIFICATIONS .................................................................................38
2
LXT901/907 Pin Assignments and Signal Descriptions
LXT901/907
PIN ASSIGNMENTS AND SIGNAL DESCRIPTIONS
Figure 1: LXT901/907 Pin Assignments
VCC1
44
43
42
41
40
39
6
5
4
3
2
1
PAUI
DON
DOP
MD1
MD0
NTH
CIN
DIN
CIP
DIP
RLD
LI
JAB
TEST
TCLK
TXD
TEN
CLKO
CLKI
COL
AUTOSEL
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
LEDC/FDE
LBK
RBIAS
GND1
RCLK
28
TPIN
TPIP
DSQE (907A) or STP (901A)
TPONB
TPONA
VCC2
GND2
TPOPA
TPOPB
PLR
RJAB
(Date Code)
(Trace Code)
(Part#)
LXT901/907PC
(Lot#)
XXXXXX
38
37
36
35
34
33
32
31
30
29
XXXX XXXX
LEDT/PDN
LEDL
RCMPT
RXD
LEDR
CD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
n/c
n/c
TPIN
TPIP
n/c
DSQE (907) or STP (901)
TPONB
TPONA
VCC2
GND2
TPOPA
TPOPB
PLR
RJAB
n/c
n/c
n/c
RLD
LI
n/c
JAB
TEST
TCLK
TXD
TEN
CLKO
CLKI
COL
AUTOSEL
n/c
n/c
n/c
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
n/c
n/c
PAUI
DIP
DIN
n/c
DOP
DON
VCCA
VCC1
CIP
CIN
NTH
MD0
MD1
n/c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(Date Code)
(Trace Code)
(Part#)
LXT901LC
(Lot#)
XXXXXX
XXXX XXXX
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
n/c
RCLK
CD
RXD
RCMPT
n/c
RBIAS
n/c
GNDA
GND1
LBK
LEDC/FDE
LEDL
LEDT/PDN
LEDR
n/c
3
LXT901/907 Universal 10BASE-T and AUI Transceivers
Table 1: LXT901/907 Signal Descriptions
PLCC
1
34
-
2
3
4
LQFP
10
56
9
11
12
13
Symbol
VCC1
VCC2
VCCA
CIP
CIN
NTH
I/O
I
I
I
I
I
I
Description
Power Inputs.
Power supply inputs of +5 volts.
(LQFP Only)
AUI Collision Pair.
Differential input to the AUI transceiver CI circuit. The
input is collision signaling or SQE.
Normal Threshold.
Selects normal or reduced threshold.
When NTH is High, the normal TP squelch threshold is in effect.
When NTH is Low, the normal TP squelch threshold is reduced by 4.5 dB.
Mode Select 0 (MD0), Mode Select 1 (MD1).
Mode select pins determine
the controller compatibility mode in accordance with Table 2.
Remote Link Down.
Output goes high to signal to the controller that the
remote port is in link down condition.
Link Test Enable.
Controls Link Integrity Test; enabled when LI = High,
disabled when LI = Low
Jabber Indicator.
Output goes High to indicate Jabber state.
Test.
For Level One internal use only.
It is recommended to tie this pin High externally.
Transmit Clock.
A 10 MHz clock output. This clock signal should be
directly connected to the transmit clock input of the controller.
Transmit Data.
Input signal containing NRZ data to be transmitted on the
network. Connect TXD directly to the transmit data output of the controller.
Transmit Enable.
Enables data transmission and starts the watchdog timer.
Synchronous to TCLK (see Test Specifications for details).
Crystal Oscillator.
A 20 MHz crystal must be connected across these pins,
or a 20 MHz clock applied at CLKI with CLKO left open.
Collision Detect.
Output which drives the collision detect input of the con-
troller.
Automatic Port Select.
When High, automatic port selection is enabled (the 901/907 defaults to the
AUI port only if TP link integrity = Fail).
When Low, manual port selection is enabled (the PAUI pin determines the
active port).
18
19
34
35
LEDR
LEDT/
PDN
LEDL
OD
OD
I
OD
I
Receive LED.
Open drain driver for the receive indicator LED. Output is
pulled Low during receive.
Transmit LED (LEDT)/Power Down (PDN).
Open drain driver for the
transmit indicator. Output is pulled Low during transmit.
If externally pulled Low, the LXT901/907 goes to power down state.
Link LED.
Open drain driver for link integrity indicator. Output is pulled
Low during link test pass.
If externally tied Low, internal circuitry is forced to “Link Pass” state and
the 901/907 will transmit link test pulses continuously.
5
6
7
8
9
10
11
12
13
14
15
16
17
14
15
18
19
21
22
23
24
25
26
27
28
29
MD0
MD1
RLD
LI
JAB
TEST
TCLK
TXD
TEN
CLKO
CLKI
COL
AUTOSEL
I
I
O
1
O
I
O
I
I
O
I
O
I
20
36
1. I/O Column Coding: I = Input, O = Output, OD = Open Drain
4
LXT901/907 Pin Assignments and Signal Descriptions
Table 1: LXT901/907 Signal Descriptions
– continued
PLCC
21
LQFP
37
Symbol
LEDC/
FDE
I/O
OD
I
Description
Collision LED (LEDC)/Full Duplex Enable (FDE).
Open drain driver for
the collision indicator pulls Low during collision. LED “On”(i.e., Low out-
put) time is extended by approximately 100 ms.
If externally tied Low, the LXT901/907 enables full duplex operation by dis-
abling the internal TP loopback and collision detection circuits in anticipa-
tion of external TP loopback or full duplex operation.
If this pin is not used, tie high or directly to V
CC
.
22
23
33
–
24
25
38
39
55
40
42
44
LBK
GND1
GND2
GNDA
RBIAS
RCMPT
I
–
–
–
I
O
Loopback.
Enables internal loopback mode.
Refer to Functional Descriptions for details.
Ground Returns.
Grounds
(LQFP Only)
Bias Control.
A 12.4 kΩ 1% resistor to ground at this pin controls operat-
ing circuit bias.
Remote Compatibility.
Output goes High to signal the controller that the
remote port is compatible with the LXT901/LXT907 remote signaling fea-
tures.
Receive Data.
Connect RXD directly to the receive data input of the con-
troller.
Carrier Detect.
An output to notify the controller of activity on the net-
work.
Receive Clock.
A recovered 10 MHz clock which is synchronous to the
received data. Connect to the controller receive clock input.
Remote Jabber.
Output goes High to indicate the remote port is in Jabber
condition.
Polarity Reverse.
Output goes High to indicate reversed polarity at the TP
input.
Twisted-Pair Transmit Pairs A & B.
Two differential driver pair outputs
(A and B) to the twisted-pair cable. The outputs are pre-equalized. Each pair
must be shorted together and tied to the transformer with a 24.9Ω 1% series
resistor to match impedance of 100Ω.
Refer to Figure 15 in the Applications Section for information on 150Ω
configurations.
26
27
28
29
30
31
36
32
35
45
46
47
51
52
53
58
54
57
RXD
CD
RCLK
RJAB
PLR
TPOPB
TPONB
TPOPA
TPONA
O
O
O
O
O
O
O
O
O
1. I/O Column Coding: I = Input, O = Output, OD = Open Drain
5
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