LXP710
HDSL Framer/Mapper for 1168 kbps Applications
Datasheet
General Description
The LXP710 is a complete HDSL framer/mapper that multiplexes and demultiplexes a framed
or unframed 2.048 Mbps E1 data stream onto two 1168 kbps HDSL lines. The LXP710 also
supports point-to-point and point-to-multipoint fractional E1 applications with 1, 2 or 3 HDSL
lines.
The LXP710 interfaces directly with the Level One SK70704/SK70707 1168 kbps HDSL data
pump and industry standard E1 Framers or Line Interface ICs. The framer/mapper is controlled
and monitored by an external microprocessor using an 8-bit Intel or Motorola compatible
parallel interface. The framer/mapper provides both programmable and 6ms interrupts
synchronized to the HDSL frame rate.
The LXP710 provides fully programmable mapping between the E1 and HDSL interfaces on
one or more loops. The LXP710 provides support for system performance monitoring with
internal CRC, FEBE and BPV error counters and the capability to inject these errors.
The framer/mapper automatically controls the synchronization between the HDSL loop timing
and the E1 payload timing using a digital PLL for E1 timing recovery and a transmitter stuffing
control circuit.
Product Features
s
s
s
s
s
s
s
Compliant with ETSI ETR-152
requirements
Interfaces with 1, 2 or 3 Level One HDSL
Data Pumps and industry standard E1
Framers or Line Interface ICs
8-bit, Intel or Motorola compatible parallel
processor interface with programmable and
6ms interrupts
User definable 10 kbps overhead channel
HDSL Overhead Management
DPLL for E1 Timing Recovery
HDSL Transmit Stuffing Control
s
s
E1 to HDSL Loop Multiplexing/
Demultiplexing
— Programmable time slot mapping
— Accepts framed or unframed E1 data
— IDLE Code Insertion provides channel
blocking in mux and demux directions
— DS0 Channel Grouping
— Loopbacks toward E1 and HDSL
interfaces
Diagnostics/Performance Monitoring
— QRSS Pattern Generation and Detection
— CRC, BPV and FEBE counters and error
generators
As of January 15, 2001, this document replaces the Level One document
known as
HDSL Framer/Mapper for 1168 kbps Applications.
Order Number:
249004-001
January 2001
Information in this document is provided in connection with Intel
®
products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXP710 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.
Datasheet
HDSL Framer/Mapper for 1168 kbps Applications — LXP710
Contents
1.0
2.0
Pin Assignments and Signal Descriptions
....................................................10
Functional Description
...........................................................................................15
2.1
2.2
2.3
2.4
2.5
Multiplexer (MX) ..................................................................................................15
Demultiplexer (DX) ..............................................................................................17
Microprocessor Interface.....................................................................................18
E1 Interface .........................................................................................................19
HDSL Interface....................................................................................................20
3.0
4.0
Register Definitions
.................................................................................................21
Application information
.........................................................................................62
4.1
4.2
4.3
4.4
Target Applications..............................................................................................62
ETSI Compliant Operation ..................................................................................62
User Definable HDSL Overhead Bits ..................................................................63
System Software Guidelines ...............................................................................65
4.4.1 Board Initialization ..................................................................................66
4.4.2 Loop Activation.......................................................................................66
4.4.3 Normal Operation ...................................................................................66
4.4.4 Diagnostic Operation..............................................................................67
4.4.5 External Communication ........................................................................67
5.0
6.0
Test Specifications
..................................................................................................71
Mechanical Specifications
....................................................................................83
Figures
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LXP710 Block Diagram ......................................................................................... 9
LXP710 Pinout Diagram......................................................................................10
MX Process .........................................................................................................16
DX Process .........................................................................................................18
E1 Interface with Loopback Switching.................................................................19
HDSL Interface....................................................................................................20
Two-Loop E1 HDSL System ..............................................................................63
Unframed Data Transport Operation...................................................................64
Point-to-Multipoint E1 HDSL System ..................................................................65
Frame Structure of Two Pair Point-to-Point System ...........................................70
E1 Interface Input Timing ....................................................................................72
E1 Interface Output Timing .................................................................................73
HDSL Interface Input Timing ...............................................................................73
HDSL Interface Output Timing ............................................................................74
Microprocessor Write Cycle—Motorola Mode.....................................................75
Microprocessor Read Cycle—Motorola Mode.....................................................76
Microprocessor Write Cycle—Intel Mode ............................................................77
Microprocessor Read Cycle—Intel Mode............................................................78
Peak Output Jitter Performance ..........................................................................79
Datasheet
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LXP710 — HDSL Framer/Mapper for 1168 kbps Applications
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Output Wander Performance .............................................................................. 80
Typical Jitter Transfer Results............................................................................. 81
Jitter Transfer Measurement Setup..................................................................... 81
Typical Jitter Tolerance Results .......................................................................... 82
Jitter Tolerance Measurement Setup .................................................................. 82
Plastic Leaded Chip Carrier Package Specification............................................ 83
Tables
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Pin Descriptions .................................................................................................. 11
Register Summary .............................................................................................. 21
Mux E1 Control Register ..................................................................................... 24
Demux E1 Control Register ................................................................................ 25
HDSL Loop Control Register............................................................................... 26
HDSL Loop 1 Overhead Control Register ........................................................... 26
HDSL Loop 2 Overhead Control Register ........................................................... 27
HDSL Loop 3 Overhead Control Register ........................................................... 28
Time Slot Grouping Table Control Register ........................................................ 28
Loop 1 Time Slot Control Byte 1 ......................................................................... 29
Loop 1 Time Slot Control Byte 2 ......................................................................... 29
Loop 1 Time Slot Control Byte 3 ......................................................................... 30
Loop 1 Time Slot Control Byte 4 ......................................................................... 30
Loop 2 Time Slot Control Byte 1 ......................................................................... 31
Loop 2 Time Slot Control Byte 2 ......................................................................... 31
Loop 2 Time Slot Control Byte 4 ......................................................................... 32
Loop 3 Time Slot Control Byte 1 ......................................................................... 32
Loop 3 Time Slot Control Byte 2 ......................................................................... 33
Loop 3 Time Slot Control Byte 3 ......................................................................... 33
Loop 3 Time Slot Control Byte 4 ......................................................................... 33
Programmable Idle Code Bytes .......................................................................... 33
QRSS Test Pattern Control Register .................................................................. 34
Frame Pulse Sync & PLL Control Register ......................................................... 34
Test Pattern Error Counter Status Register ........................................................ 35
Demux Power Status Register ............................................................................ 35
Demux HDSL Repeater Present Status Register ............................................... 36
Demux Loss of Signal Status Register................................................................ 36
Loop Reversal Status Register ........................................................................... 36
General Interrupt Enable Register ...................................................................... 37
General Interrupt Status Register ....................................................................... 37
6ms Interrupt Enable Register ............................................................................ 38
6ms Interrupt Status Register ............................................................................. 38
Indicator Bits & Triple Echo EOC Enable Register ............................................. 39
Indicator Bits & Triple EOC Status Register........................................................ 39
Global Control Register....................................................................................... 40
PLL Band Width Control (High Byte).................................................................. 40
PLL Band Width Control (Low Byte) .................................................................. 41
Demux Restart Counter ..................................................................................... 41
Mux Loop 1 Z Bits (LSB) ..................................................................................... 41
Mux Loop 1 Z Bits ............................................................................................... 41
Mux Loop 1 Z Bits ............................................................................................... 42
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Datasheet
HDSL Framer/Mapper for 1168 kbps Applications — LXP710
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Mux Loop 1 Z Bits ...............................................................................................42
Mux Loop 1 Z Bits ...............................................................................................42
Mux Loop 1 Z Bits (MSB) ....................................................................................42
Mux Loop 1 EOC Message (High Byte) ..............................................................42
Mux Loop 1 EOC Message (Low Byte) ...............................................................43
Mux Loop 1 UIB Bits............................................................................................43
Demux Loop 1 Z Bits (LSB).................................................................................43
Demux Loop 1 Z Bits...........................................................................................44
Demux Loop 1 Z Bits...........................................................................................44
Demux Loop 1 Z Bits...........................................................................................44
Demux Loop 1 Z Bits...........................................................................................44
Demux Loop 1 Z Bits (MSB)................................................................................44
Demux Loop 1 EOC Message (High Byte)..........................................................45
Demux Loop 1 EOC Message (Low byte)...........................................................45
Demux Loop 1 UIB Bits .......................................................................................45
Demux Loop 1 CRC Error Count.........................................................................46
Demux Loop 1 FEBE Error Count .......................................................................46
Demux Loop 1 BPV Error Count .........................................................................46
Loop 1 QRSS Test Pattern Error Counter (High byte) ........................................47
Loop 1 QRSS Test Pattern Error Counter (Low).................................................47
Loop 1 Mux Restart Counter ..............................................................................47
Mux Loop 2 Z Bits (LSB) .....................................................................................47
Mux Loop 2 Z Bits ...............................................................................................48
Mux Loop 2 Z Bits ...............................................................................................48
Mux Loop 2 Z Bits ...............................................................................................48
Mux Loop 2 Z Bits ...............................................................................................48
Mux Loop 2 Z Bits (MSB) ....................................................................................48
Mux Loop 2 EOC Message (High byte)...............................................................49
Mux Loop 2 EOC Message (Low byte) ...............................................................49
Mux Loop 2 UIB Bits............................................................................................49
Demux Loop 2 Z Bits (LSB).................................................................................50
Demux Loop 2 Z Bits...........................................................................................50
Demux Loop 2 Z Bits...........................................................................................50
Demux Loop 2 Z Bits...........................................................................................50
Demux Loop 2 Z Bits...........................................................................................50
Demux Loop 2 Z Bits (MSB)................................................................................51
Demux Loop 2 EOC Message (High byte) ..........................................................51
Demux Loop 2 EOC Message (Low byte)...........................................................51
Demux Loop 2 UIB Bits .......................................................................................51
Demux Loop 2 CRC Error Count.........................................................................52
Demux Loop 2 FEBE Error Count .......................................................................52
Demux Loop 2 BPV Error Count .........................................................................53
Loop 2 QRSS Test Pattern Error Counter (High byte) ........................................53
Loop 2 QRSS Test Pattern Error Counter (Low byte) .........................................53
Loop 2 Mux Restart Counter ..............................................................................53
Mux Loop 3 Z Bits (LSB) .....................................................................................54
Mux Loop 3 Z Bits ...............................................................................................54
Mux Loop 3 Z Bits ...............................................................................................54
Mux Loop 3 Z Bits ...............................................................................................54
Mux Loop 3 Z Bits ...............................................................................................55
Datasheet
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