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DPSD32MX4RY5-DP-XX122I

Description
Synchronous DRAM Module, 32MX4, 12ns, CMOS, LEADLESS, STACK, TSOP-54
Categorystorage    storage   
File Size413KB,2 Pages
ManufacturerB&B Electronics Manufacturing Company
Download Datasheet Parametric View All

DPSD32MX4RY5-DP-XX122I Overview

Synchronous DRAM Module, 32MX4, 12ns, CMOS, LEADLESS, STACK, TSOP-54

DPSD32MX4RY5-DP-XX122I Parametric

Parameter NameAttribute value
MakerB&B Electronics Manufacturing Company
Parts packaging codeDMA
package instruction,
Contacts54
Reach Compliance Codeunknown
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time12 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-XDMA-N54
memory density134217728 bit
Memory IC TypeSYNCHRONOUS DRAM MODULE
memory width4
Number of functions1
Number of ports1
Number of terminals54
word count33554432 words
character code32000000
Operating modeSYNCHRONOUS
organize32MX4
Package body materialUNSPECIFIED
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Certification statusNot Qualified
self refreshYES
Nominal supply voltage (Vsup)3.3 V
surface mountNO
technologyCMOS
Terminal formNO LEAD
Terminal locationDUAL
32Mx4, 7.5 - 15ns, P12, M-Densus
30A181-02
H
128 Megabit Synchronous DRAM
DPSD32MX4RY5
DESCRIPTION:
The LP-Stack™ series is a family of interchangeable memory modules. The 128 Megabit SDRAM is a member of this
family which utilizes the new and innovative space saving TSOP stacking technology. The modules are constructed
with 16 Meg x 4 SDRAMs.
This 64 Megabit based LP-Stack™ module, the DPSD32MX4RY5 has been designed to fit in the same footprint as the
16 Meg x 4 SDRAM TSOP monolithic and 64 Megabit SDRAM based family of LP-Stack™ modules. This allows the
memory board designer to upgrade the memory in their products without redesigning the memory board, thus saving
time and money.
FEATURES:
Configuration Available:
32 Meg x 4 (2 Banks of 4M x 4 x 4 bits)
Clock Frequency:
66
[1]
, 83
[1]
, 100, 125
[2]
, 133
[2]
MHz (max.)
PC100 and PC133 Compatible
3.3V Supply
LVTTL Compatible I/O
Four Bank Operation
Programmable Burst Type, Burst Length,
and CAS Latency
4096 Cycles / 64 ms
Auto and Self Refresh
Package: TSOP Leadless Stack
NOTES:
[1] Available in Military and Industrial Temperature Ranges Only.
[2] Available in Commercial Temperature Range Only.
PIN-OUT DIAGRAM
PIN NAMES
A0 - A11
BA0, BA1
DQ0 - DQ3
CAS
RAS
WE
DQM
CKE
CLK
CS0-CS1
V
CC
/V
SS
V
CCQ
/V
SSQ
N.C.
30A181-02
REV. J
Row Address:
A0 - A11
Column Address: A0 - A9
Bank Select Address
Data In / Data Out
Column Address Strobes
Row Address Enables
Data Write Enable
Data Input/Output Mask
Clock Enable
System Clock
Chip Selects
Power Supply/Ground
Data Output Power/Ground
No Connect
FUNCTIONAL BLOCK DIAGRAM
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
1

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