128K x 8 Bit 5V EEPROM
FEATURES
•
Access Time: 120ns
•
Simple Byte and Page Write
—Single 5V Supply
—No External High Voltages or VPP Control Circuits
FT28C010-xxxxx-X
DESCRIPTION
The
Force FT28C010
is a 128K x 8 E
2
PROM, fabricated
with, high performance, floating gate
CMOS technology.
Like
most Force
programmable nonvolatile
memories
the
FT28C010
is a 5V only device. The
FT28C010
features the JEDEC approved pinout for byte-
wide memories, compatible with industry standard
EPROMs.
The
FT28C010
supports a 256-byte page write operation,
effectively providing a 19
µs/byte
write cycle and en-
abling the entire memory to be typically written in less
than 2.5 seconds. The
FT28C010
also features
DATA
Polling and Toggle Bit Polling, system software support
schemes used to indicate the early completion of a write
cycle. In addition, the
FT28C010
supports Software Data
Protection option.
Force
E
2
PROMs are designed and tested for applica-
tions requiring extended endurance. Data retention is
specified to be greater than 100 years.
•
•
•
•
•
•
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
Low Power CMOS:
—Active: 50mA
—Standby: 500
µ
A
Software Data Protection
—Protects Data Against System Level
Inadvertant Writes
High Speed Page Write Capability
Highly Reliable Cell
—Endurance: 100,000 Write Cycles
—Data Retention: 100 Years
Early End of Write Detection
—DATA Polling
—Toggle Bit Polling
-X Manufactured using Xicor Die
FT28C010-xxxxx-AT
128K x 8 Bit 5V EEPROM
FEATURES
•
Fast Read Access Time 120ns
•
Automatic Page Write Operation
Internal Address and Data Latches for
128-Bytes Internal Control Timer
•
Fast Write Cycle Time
Page Write Cycle Time - 10 ms Maximum
1 to 128-Byte Page Write Operation
•
Low Power Dissipation
80 mA Active Current
300 µA CMOS Standby Current
•
Hardware and Software Data Protection
•
DATA Polling for End of Write Detection
•
High Reliability CMOS Technology
Endurance: 104
Data Retention: 10 Years
•
Single 5V
±
10% Supply
•
CMOS and TTL Compatible Inputs and Outputs
•
-
AT Manufactured using Atmel Die
DESCRIPTION
The FT28C010 is a high-performance Electrically Erasable
and Programmable Read Only Memory. Its one megabit of
memory isorganised as 131,072 words by 8 bits.
Manufactured with advanced nonvolatile CMOS technology,
the device offersaccess times to 120 ns with power dissipa-
tion of just 440 mW. When the device isdeselected, the CMOS
standby current is less than 300 mA. (Cont)
Rev 1.3
1/31
March 2014
FT28C010-xxxxx-X
DEVICE OPERATION
Read
Read operations are initiated by both
OE
and
CE
LOW.
The read operation is terminated by either
CE
or
OE
returning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The data
bus will be in a high impedance state when either
OE
or
CE
is HIGH.
Write
Write operations are initiated when both
CE
and
WE
are
LOW and
OE
is HIGH. The
FT28C010
supports both a
CE
and
WE
controlled write cycle. That is, the address
is latched by the falling edge of either
CE
or
WE,
which-
ever occurs last. Similarly, the data is latched internally by
the rising edge of either
CE
or
WE,
whichever occurs first.
A byte write operation, once initiated, will automatically
continue to completion, typically within 5ms.
Page Write Operation
The page write feature of the
FT28C010
allows the entire
memory to be written in 5 seconds. Page write allows
two to two hundred fifty-six bytes of data to be consecu-
tively written to the
FT28C010
prior to the commence-
ment of the internal programming cycle. The host can
fetch data from another device within the system during
a page write operation (change the source address), but
the page address (A
8
through A
16
) for each subsequent
valid write cycle to the part during this operation must be
the same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to two hundred fifty six bytes
in the same manner as the first byte was written. Each
successive byte load cycle, started by the
WE
HIGH to
LOW transition, must begin within 100
µs
of the falling
edge of the preceding
WE.
If a subsequent
WE
HIGH to
LOW transition is not detected within 100
µs,
the internal
automatic programming cycle will commence. There is
no page write window limitation. Effectively the page
write window is infinitely wide, so long as the host
continues to access the device within the byte load cycle
time of 100µs.
Write Operation Status Bits
The
FT28C010
provides the user two write operation
status bits. These can be used to optimise a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
I/O
DP
TB
5
4
3
2
1
0
RESERVED
TOGGLE BIT
DATA POLLING
DATA
Polling (I/O
7
)
The
FT28C010
features
DATA
Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed.
DATA
Polling allows a simple
bit test operation to determine the status of the
FT28C010,
eliminating additional interrupt inputs or external hard-
ware. During the internal programming cycle, any at-
tempt to read the last byte written will produce the
complement of that data on I/O
7
(i.e., write data = 0xxx
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O
7
will reflect true data. Note: If the
FT28C010
is in the protected state and an illegal write
operation is attempted
DATA
Polling will not operate.
Toggle Bit (I/O
6
)
The
FT28C010
also provides another method for deter-
mining when the internal write cycle is complete. During
the internal programming cycle, I/O
6
will toggle from
HIGH to LOW and LOW to HIGH on subsequent at-
tempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
Rev 1.3
4/31
March 2014
Power technology
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