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FM24C16ULEMT8

Description
EEPROM, 2KX8, Serial, CMOS, PDSO8, TSSOP-8
Categorystorage    storage   
File Size100KB,14 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Download Datasheet Parametric View All

FM24C16ULEMT8 Overview

EEPROM, 2KX8, Serial, CMOS, PDSO8, TSSOP-8

FM24C16ULEMT8 Parametric

Parameter NameAttribute value
MakerFairchild
Parts packaging codeSOIC
package instructionTSSOP, TSSOP8,.25
Contacts8
Reach Compliance Codeunknown
ECCN codeEAR99
Maximum clock frequency (fCLK)0.1 MHz
Data retention time - minimum40
Durability1000000 Write/Erase Cycles
I2C control byte1010MMMR
JESD-30 codeR-PDSO-G8
length4.4 mm
memory density16384 bit
Memory IC TypeEEPROM
memory width8
Number of functions1
Number of terminals8
word count2048 words
character code2000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize2KX8
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP8,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Parallel/SerialSERIAL
power supply3/5 V
Certification statusNot Qualified
Maximum seat height1.2 mm
Serial bus typeI2C
Maximum standby current0.00001 A
Maximum slew rate0.001 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)2.7 V
Nominal supply voltage (Vsup)3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
width3 mm
Maximum write cycle time (tWC)15 ms
FM24C16U/17U – 16K-Bit Standard 2-Wire Bus Interface Serial EEPROM
August 2000
FM24C16U/17U – 16K-Bit Standard 2-Wire Bus
Interface Serial EEPROM
General Description
The FM24C16U/17U devices are 16,384 bits of CMOS non-
volatile electrically erasable memory. These devices conform to
all specifications in the Standard IIC 2-wire protocol. They are
designed to minimize device pin count and simplify PC board
layout requirements.
The upper half (upper 8Kbit) of the memory of the FM24C17U can
be write protected by connecting the WP pin to V
CC
. This section of
memory then becomes unalterable unless WP is switched to V
SS
.
This communications protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).
The Standard IIC protocol allows for a maximum of 16K of
EEPROM memory which is supported by the Fairchild family in
2K, 4K, 8K, and 16K devices, allowing the user to configure the
memory as the application requires with any combination of
EEPROMs. In order to implement higher EEPROM memory
densities on the IIC bus, the Extended IIC protocol must be used.
(Refer to the FM24C32 or FM24C65 datasheets for more informa-
tion.)
Fairchild EEPROMs are designed and tested for applications requir-
ing high endurance, high reliability and low power consumption.
Features
I
Extended operating voltage 2.7V – 5.5V
I
400 KHz clock frequency (F) at 2.7V - 5.5V
I
200µA active current typical
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
I
IIC compatible interface
– Provides bi-directional data transfer protocol
I
Sixteen byte page write mode
– Minimizes total write time per byte
I
Self timed write cycle
Typical write cycle time of 6ms
I
Hardware Write Protect for upper half (FM24C17U only)
I
Endurance: 1,000,000 data changes
I
Data retention greater than 40 years
I
Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP
I
Available in three temperature ranges
- Commercial: 0° to +70°C
- Extended (E): -40° to +85C
- Automotive (V): -40° to +125°C
Block Diagram
VCC
VSS
WP
H.V. GENERATION
TIMING &CONTROL
START
STOP
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER
E2PROM
ARRAY
SDA
SCL
XDEC
WORD
ADDRESS
COUNTER
R/W
YDEC
CK
DIN
DATA REGISTER
DOUT
© 2000 Fairchild Semiconductor International
FM24C16U/17U Rev. A.3
1
www.fairchildsemi.com

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