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FT61024-25P3C

Description
Standard SRAM, 128KX8, 25ns, CMOS, PDIP32, 0.300 INCH, PLASTIC, DIP-32
Categorystorage    storage   
File Size311KB,15 Pages
ManufacturerForce Technologies Ltd.
Download Datasheet Parametric View All

FT61024-25P3C Overview

Standard SRAM, 128KX8, 25ns, CMOS, PDIP32, 0.300 INCH, PLASTIC, DIP-32

FT61024-25P3C Parametric

Parameter NameAttribute value
MakerForce Technologies Ltd.
Parts packaging codeDIP
package instructionDIP,
Contacts32
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time25 ns
JESD-30 codeR-PDIP-T32
length40.64 mm
memory density1048576 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize128KX8
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
width7.62 mm
FT61024
HIGH SPEED 128K x 8
DUAL CHIP ENABLE
CMOS STATIC RAM
FEATURES
High Speed (Equal Access and Cycle Times)
— 15/20/25/35 ns (Commercial)
— 20/25/35/45 ns (Industrial)
— 20/25/35/45/55/70/85/100/120 ns (Military)
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using
CE
1,
CE
2
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast t
OE
Automatic Power Down
Packages
—32-Pin 300 mil DIP and SOJ
—32-Pin 400 mil SOJ
—32-Pin 600 mil Ceramic DIP
—32-Pin 400 mil Ceramic DIP
—32-Pin Solder Seal Flatpack
—32-Pin LCC (450 x 550 mil)
—32-Pin Ceramic SOJ
DESCRIPTION
The FT61024 is a 1,048,576-bit high-speed CMOS
static RAM organised as 128Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 15 nanoseconds permit greatly en-
hanced system operating speeds. CMOS is utilised to
reduce power consumption to a low level.The FT61024
is a member of a family ofForce Ram products offer-
ing fast access times.
The FT61024 device provides asynchronous opera-
tions with matching access and cycle times. Memory
locations are specified on address pins A
0
to A
16
.
Reading is accomplished by device selection
CE
1
low
(
and CE
2
high) and output enabling (
OE)
while write
enable (WE) remains HIGH. By presenting the ad-
dress under these conditions, the dat a in the ad-
dressed memory location is presented on the dat a
input/output pins. The input/output pins st ay in the
HIGH Z state when either
CE
1
or
OE
is HIGH or
WE
or CE
2
is LOW.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP (P300, C10, C11),
SOJ (J300, J400, CJ1),
SOLDER SEAL
FLATPACK (FS-3) SIMILAR
LCC (L6)
REV 1
1/15
2008
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