HY27SF081G2M-SPEB datasheet, PDF

Datasheet> All Categories > storage> storage> HY27SF081G2M-SPEB

HY27SF081G2M-SPEB: DescriptionFlash, 128MX8, 30ns, PDSO48, 12 X 17 MM, 0.65 MM HEIGHT, LEAD FREE, USOP1-48; Categorystorage storage; File Size425KB，48 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/; Environmental Compliance

Download Datasheet Parametric View All

HY27SF081G2M-SPEB Overview

Flash, 128MX8, 30ns, PDSO48, 12 X 17 MM, 0.65 MM HEIGHT, LEAD FREE, USOP1-48

HY27SF081G2M-SPEB Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	SK Hynix
Parts packaging code	SOIC
package instruction	VSSOP, TSSOP48,.71,20
Contacts	48
Reach Compliance Code	compliant
ECCN code	3A991.B.1.A
Maximum access time	30 ns
command user interface	YES
Data polling	NO
JESD-30 code	R-PDSO-G48
length	15.4 mm
memory density	1073741824 bit
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of departments/size	1K
Number of terminals	48
word count	134217728 words
character code	128000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-25 °C
organize	128MX8
Package body material	PLASTIC/EPOXY
encapsulated code	VSSOP
Encapsulate equivalent code	TSSOP48,.71,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH
page size	2K words
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	1.8 V
Programming voltage	1.8 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	0.65 mm
Department size	128K
Maximum standby current	0.00005 A
Maximum slew rate	0.015 mA
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	20
switch bit	NO
type	SLC NAND TYPE
width	12 mm

Preview

Download Datasheet

View All

HY27UF(08/16)1G2M Series

HY27SF(08/16)1G2M Series

1Gbit (128Mx8bit / 64Mx16bit) NAND Flash

Document Title

1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory

Revision History

Revision

No.

0.0

1) Initial Draft.

1) Correct Fig.10 Sequential out cycle after read

2) Add the text to Fig.1, Table.1, Table.2

- text : IO15 - IO8 (x16 only)

3) Delete ‘3.2 Page program NOTE 1.

- Note : if possible it is better to remove this constrain

4) Change the text ( page 10,13, 45)

- 2.2 Address Input : 28 Addresses -> 27 Addresses

- 3.7 Reset : Fig.29 -> Fig.30

- 5.1 Automatic page read after power up : Fig.30 -> Fig.29

5) Add 5.3 Addressing for program operation & Fig.34

1) Change TSOP, WSOP, FBGA package dimension & figures.

- Change TSOP, WSOP, FBGA package mechanical data

- Change FBGA thickness (1.2 -> 1.0 mm)

2) Correct TSOP, WSOP Pin configurations.

- 38th NC pin has been changed Lockpre(figure

3,4)

3) Edit figure 15,19 & table 4

4) Add Bad Block Management

5) Change Device Identifier 3rd Byte

- 3rd Byte ID is changed. (reserved -> don't care)

- 3rd Byte ID table is deleted.

1) Add Errata

tCLS

Specification

Relaxed value

tCLH

tWP

tALS

tALH

tDS

tWC

History

Draft Date

Aug. 2004

Remark

Preliminary

0.1

Sep. 2004

Preliminary

0.2

Oct. 2004

Preliminary

0.3

0.4

2) LOCKPRE is changed to PRE.

- Texts, Table, Figures are changed.

3) Add Note.4 (table.14)

4) Block Lock Mechanism is deleted.

- Texts, Table, figures are deleted.

5) Add Application Note(Power-On/Off Sequence & Auto Sleep mode.)

- Texts & Figures are added.

6) Edit the figures. (#10~25)

1) Change AC characteristics(tREH)

before: 20ns -> after: 30ns

2) Edit Note.1 (page. 21)

3) Edit the Application note 1,2

4) Edit The Address cycle map (x8, x16)

Nov.29 2004

Preliminary

Jan.19 2005

Preliminary

Rev 1.1 / Nov. 2005

HY27UF(08/16)1G2M Series

HY27SF(08/16)1G2M Series

1Gbit (128Mx8bit / 64Mx16bit) NAND Flash

1. SUMMARY DESCRIPTION

The HYNIX HY27(U/S)F(08/16)1G2M series is a 128Mx8bit with spare 4Mx8 bit capacity. The device is offered in 1.8V

Vcc Power Supply and in 3.3V Vcc Power Supply.

Its NAND cell provides the most cost-effective solution for the solid state mass storage market.

The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old

data is erased.

The device contains 1024 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected

Flash cells.

A program operation allows to write the 2112-byte page in typical 300us and an erase operation can be performed in

typical 2ms on a 128K-byte(X8 device) block.

Data in the page mode can be read out at 50ns cycle time per word. The I/O pins serve as the ports for address and

data input/output as well as command input. This interface allows a reduced pin count and easy migration towards dif-

ferent densities, without any rearrangement of footprint.

Commands, Data and Addresses are synchronously introduced using CE#, WE#, ALE and CLE input pin.

The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where

required, and internal verification and margining of data.

The modifying can be locked using the WP# input pin.

The output pin RB# (open drain buffer) signals the status of the device during each operation. In a system with mul-

tiple memories the RB# pins can be connected all together to provide a global status signal.

Even the write-intensive systems can take advantage of the HY27(U/S)F(08/16)1G2M extended reliability of 100K pro-

gram/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.

Optionally the chip could be offered with the CE# don’t care function. This option allows the direct download of the

code from the NAND Flash memory device by a microcontroller, since the CE# transitions do not stop the read opera-

tion.

The copy back function allows the optimization of defective blocks management: when a page program operation fails

the data can be directly programmed in another page inside the same array section without the time consuming serial

data insertion phase.

The cache program feature allows the data insertion in the cache register while the data register is copied into the

flash array. This pipelined program operation improves the program throughput when long files are written inside the

memory.

A cache read feature is also implemented. This feature allows to dramatically improve the read throughput when con-

secutive pages have to be streamed out.

This device includes also extra features like OTP/Unique ID area, Automatic Read at Power Up, Read ID2 extension.

The HYNIX HY27(U/S)F(08/16)1G2M series is available in 48 - TSOP1 12 x 20 mm , 48 - USOP1 12 x 17 mm.

1.1 Product List

PART NUMBER

HY27SF081G2M

HY27SF161G2M

HY27UF081G2M

HY27UF161G2M

ORIZATION

x16

VCC RANGE

1.70 - 1.95 Volt

48TSOP1 / 48USOP1

2.7V - 3.6 Volt

PACKAGE

Rev 1.1 / Nov. 2005

Recommended Resources

How does a fuse resistor work?

OTL low frequency power amplifier circuit

Wiring using broken wire fluorescent lamps a

Microphone hybrid circuit

Square wave generator with variable pulse width

800Hz Wien Bridge Oscillator Circuit

Seeking LED high-power driver chip specifications and sampling issues: 1. Parameter requirements: IN dc12v or 24V OUT: 12-20V 4A 50-60W, PWM dimming2. Key point: Since the lamp is sealed, it is not possible to see whether the lamp is working properly from the outside. Wh...; sud0 LED Zone

Received a big school bag: I received the gift, thanks to the forum, the school bag is really big and thick, and a one-yuan coin is attached for size comparison: lol...; sjtitr Talking

Please help me, I got this error when I was drawing the board.: It works fine after I ticked the Allow short circuit option. Why?...; 西里古1992 PCB Design

How to modify some configuration parameters in modem properties? Urgent, waiting online!!: I've been experimenting with using wince to dial up to the Internet recently. The parts related to creating a connection and dialing up to the Internet have been completed through the relevant functio...; zxzxzxz Embedded System

DSP---C674x Framework Overview: 1. Overview The overall framework of TMS320C674x DSP (megamodule) includes the following subsystems: C674x floating-point/fixed-point DSP CPU First level program (L1P) memory space controller (excludi...; Aguilera DSP and ARM Processors

Can a serial DAC chip directly amplify analog quantities?: Can the serial DAC chip be controlled by a single-chip microcomputer to directly amplify the analog quantity and achieve adjustable gain?...; sungang1021 Analog electronics

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components