TECHNICAL NOTE
High Reliability Series Serial EEPROM Series
I C BUS
Serial EEPROMs
BR24L□□-W Series
BR24L01A-W, BR24L02-W, BR24L04-W, BR24L08-W,
BR24L16-W, BR24L32-W, BR24L64-W
2
BR24S□□□-W Series
BR24S16-W, BR24S32-W, BR24S64-W, BR24S128-W, BR24S256-W
ROHM's series of serial EEPROMs represent the highest level of reliability on the market. A double cell structure provides a
failsafe method of data reliability, while a double reset function prevents data miswriting. In addition, gold pads and gold
wires are used for internal connections, pushing the boundaries of reliability to the limit.
BR24L□□-W Series assort 1Kbit½64Kbit. BR24S□□□-W Series are possible to operate at high speed in low voltage and
assort 16Kbit½256Kbit.
Contents
BR24L□□-W
Series
BR24L01A-W, BR24L02-W, BR24L04-W, BR24L08-W,
BR24L16-W, BR24L32-W, BR24L64-W
・・・・P2
BR24S□□□-W
Series
BR24S16-W, BR24S32-W, BR24S64-W,
BR24S128-W, BR24S256-W
・・・・P17
Sep. 2008
I
2
C BUS Serial EEPROMs
BR24L□□-W Series
BR24L01A-W, BR24L02-W, BR24L04-W, BR24L08-W,
BR24L16-W, BR24L32-W, BR24L64-W
●Description
2
BR24L□□-W series is a serial EEPROM of I C BUS interface method.
●Features
2
・
Completely conforming to the world standard I C BUS. All controls available by 2 ports of serial clock(SCL) and serial
data(SDA)
・
Other devices than EEPROM can be connected to the same port, saving microcontroller port
*1
・
1.8V~5.5V single power source action most suitable for battery use
・
Page write mode useful for initial value write at factory shipment
・
Highly reliable connection by Au pad and Au wire
・
Auto erase and auto end function at data rewrite
・
Low current consumption
*2
At write operation (5V)
: 1.2mA (Typ.)
At read operation (5V)
: 0.2mA (Typ.)
At standby operation (5V) : 0.1μA (Typ.)
・
Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
*3
・
SOP8/SOP-J8/SSOP-B8/TSSOP-B8/MSOP8/TSSOP-B8J/VSON008X2030 compact package
・
Data rewrite up to 1,000,000 times
・
Data kept for 40 years
Page write
・
Noise filter built in SCL / SDA terminal
・
Shipment data all address FFh
*1
*2
*3
BR24L02-W、BR24L16-W、BR24L32-W : 1.7½5.5V
BR24L32-W、BR24L64-W : 1.5mA
Refer to following list
Number of
Pages
Product
number
8Byte
BR24L01A-W
BR24L02-W
16Byte
BR24L04-W
BR24L08-W
BR24L16-W
32Byte
BR24L32-W
BR24L64-W
●BR24L
series
Capacity
Bit format
Type
Power source
Voltage
SOP8
F
SOP-J8
FJ
SSOP-B8 TSSOP-B8
FV
FVT
MSOP8
FVM
TSSOP-B8J
FVJ
VSON008
X2030
NUX
1Kbit
2Kbit
4Kbit
8Kbit
16Kbit
32Kbit
64Kbit
128×8
256×8
512×8
1K×8
2K×8
4K×8
8K×8
BR24L01A-W
BR24L02-W
BR24L04-W
BR24L08-W
BR24L16-W
BR24L32-W
BR24L64-W
1.8½5.5V
1.7½5.5V
1.8½5.5V
1.8½5.5V
1.7½5.5V
1.7½5.5V
1.8½5.5V
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
2/32
●Absolute
maximum ratings (Ta=25℃)
Parameter
Impressed voltage
symbol
V
CC
Limits
－0.3½+6.5
450 (SOP8)
*1
450 (SOP-J8)
*2
300 (SSOP-B8)
*3
330 (TSSOP-B8)
*4
310 (MSOP8)
*5
310 (TSSOP-B8J)
*6
300 (VSON008X2030)
*7
Unit
V
●Memory
cell characteristics (Ta=25℃, Vcc=1.8½5.5V)
*1
Parameter
Number of data rewrite times
*2
mW
Data hold years
○Shipment
data all address FFh
*2
Limits
Min.
1,000,000
40
*1
*2
Typ.
－
－
Max.
－
－
Unit
Times
Years
Permissible
dissipation
Pd
BR24L02/16/32-W : 1.7~5.5V
Not 100% TESTED
Storage
Tstg
－65½+125
temperature range
Action
Topr
－40½+85
temperature range
Terminal voltage
－
－0.3½Vcc+1.0
*1,*2
)
*3,*7
)
When using at Ta=25℃ or higher, 4.5mW
(
, 3.0mW
(
3.3mW
( )
,3.1mW
(
*4
*5,*6)
℃
℃
V
●Recommended
operating conditions
Parameter
Power source voltage
Input voltage
Symbol
Vcc
V
IN
*1
Limits
1.8½5.5
0½Vcc
*1
Unit
V
to be reduced per 1℃
BR24L02/16/32-W : 1.7~5.5V
●Electrical
characteristics (Unless otherwise specified, Ta=－40½+85℃, V
CC
=1.8½5.5V)
*1
Parameter
“HIGH” input voltage 1
“LOW” input voltage 1
“HIGH” input voltage 2
“LOW” input voltage 2
“HIGH” input voltage 3
*3
“HIGH” input voltage 3
*4
“LOW” input voltage 3
*2
“LOW” output voltage 1
“LOW” output voltage 2
Input leak current
Output leak current
Current consumption at
action
Symbol
V
IH1
V
IL1
V
IH2
V
IL2
V
IH3
V
IH3
V
IL3
V
OL1
V
OL2
I
LI
I
LO
I
CC1
I
CC2
I
SB
Min.
0.7Vcc
－0.3
*2
0.8Vcc
－0.3
*2
0.8Vcc
0.9Vcc
－0.3
－
－
－1
－1
－
－
－
Limits
Typ.
－
－
－
－
－
－
－
－
－
－
－
－
－
－
*1
*5
Max.
Vcc +1.0
*2
0.3 Vcc
Vcc +1.0
*2
0.2 Vcc
Vcc +1.0
Vcc +1.0
0.1 Vcc
0.4
0.2
1
1
2.0
*5
3.0
*6
0.5
2.0
Unit
V
V
V
V
V
V
V
V
V
μA
μA
mA
mA
μA
Conditions
2.5≦Vcc≦5.5V
2.5≦Vcc≦5.5V
1.8≦Vcc＜2.5V
1.8≦Vcc＜2.5V
1.7≦Vcc＜1.8V
1.7≦Vcc＜1.8V
1.7≦Vcc＜1.8V
I
OL
=3.0mA, 2.5V≦Vcc≦5.5V, (SDA)
I
OL
=0.7mA, 1.7V≦Vcc＜2.5V, (SDA)
V
IN
=0V½Vcc
V
OUT
=0V½Vcc, (SDA)
Vcc=5.5V,f
SCL
=400kHz, t
WR
=5ms,
Byte write, Page write
Vcc=5.5V,f
SCL
=400kHz
Random read, current read, sequential read
Vcc=5.5V, SDA・SCL=Vcc
A0, A1, A2=GND, WP=GND
Standby current
◎
Radiation resistance design is not made.
BR24L02/16/32-W : 1.7½5.5V,
*2
BR24L16/32-W,
*3
BR24L02/16-W,
*4
BR24L32-W
BR24L01A/02/04/08/16-W,
*6
BR24L32/64-W
●Action
timing characteristics
Parameter
(Unless otherwise specified, Ta=
－
40½+85℃, V
CC
=1.8½5.5V)
*1
Symbol
fSCL
tHIGH
tLOW
tR
tF
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tPD
tDH
tSU:STO
tBUF
tWR
tI
tHD:WP
tSU:WP
tHIGH:WP
Min.
－
0.6
1.2
－
－
0.6
0.6
0
100
0.1
0.1
0.6
1.2
－
－
0
0.1
1.0
FAST-MODE
2.5V≦Vcc≦5.5V
Typ.
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
STANDARD-MODE
1.8V≦Vcc≦5.5V
Unit
Min.
Typ.
Max.
－
－
100
kHz
4.0
－
－
μs
4.7
－
－
μs
－
－
1.0
μs
－
－
0.3
μs
4.0
－
－
μs
4.7
－
－
μs
0
－
－
ns
250
－
－
ns
0.2
－
3.5
μs
0.2
－
－
μs
4.7
－
－
μs
4.7
－
－
μs
－
－
5
ms
－
－
0.1
μs
0
－
－
ns
0.1
－
－
μs
1.0
－
－
μs
*1
BR24L02/16/32-W : 1.7½5.5V
*2
Not 100% tested
SCL frequency
Data clock “HIGH“ time
Data clock “LOW“ time
SDA, SCL rise time
*2
SDA, SCL fall time
*2
Start condition hold time
Start condition setup time
Input data hold time
Input data setup time
Output data delay time
Output data hold time
Stop condition setup time
Bus release time before transfer start
Internal write cycle time
Noise removal valid period (SDA, SCL terminal)
WP hold time
WP setup time
WP valid time
Max.
400
－
－
0.3
0.3
－
－
－
－
0.9
－
－
－
5
0.1
－
－
－-
●FAST-MODE
and STANDARD-MODE
FAST-MODE and STANDARD-MODE are of same actions, and mode is changed. They are distinguished by action
speeds. 100kHz action is called STANDARD-MODE, and 400kHz action is called FAST-MODE. This action frequency is
the maximum action frequency, so 100kHz clock may be used in FAST-MODE. When power source voltage goes down,
action at high speed is not carried out, therefore, at Vcc=2.5V½5.5V , 400kHz, namely, action is made in FASTMODE.
(Action is made also in STANDARD-MODE) Vcc=1.8V~2.5V is only action in 100kHz STANDARD-MODE.
3/32
●Sync
data input / output timing
tR
SCL
tHD:STA
SDA
(入力)
(input)
tBUF
(output)
(出力)
tF
tHIGH
SCL
tSU:DAT
tLOW
tHD:DAT
DATA(1)
SDA
D1
D0
ACK
DATA(n)
ACK
½WR
tPD
tDH
SDA
WP
Stop condition
ストップコンディション
○Input
read at the rise edge of SCL
○Data
output in sync with the fall of SCL
tSU：WP
½HD：WP
Fig.1-(a) Sync data input / output timing
SCL
tSU:STA
SDA
Fig.1-(d) WP timing at write execution
SCL
tHD:STA
tSU:STO
DATA(1)
SDA
D1
D0
ACK
DATA(n)
ACK
tHIGH:WP
tWR
START BIT
STOP BIT
WP
Fig.1-(b) Start-stop bit timing
○At
write execution, in the area from the D0 taken clock rise of the first
DATA(1), to tWR, set WP=“LOW”.
○By
setting WP “HIGH” in the area, write can be cancelled.
When it is set WP=“HIGH” during tWR, write is forcibly ended, and data of
address under access is not guaranteed, therefore write it once again.
½WR
Stop condition
Start condition
SCL
SDA
D0
Write data
ACK
(n-th
address)
Fig.1-(c) Write cycle timing
Fig.1-(e) WP timing at write cancel
●Block
diagram
*2
A0
1
*1
1Kbit~64Kbit EEPROM array
7bit 11bit
8bit 12bit
9bit 13b
it
10bi
t
8
8bit
Vcc
*2
A1
2
Address
decoder
*1
7bit 11bit
8bit 12bit
9bit 13b
it
10bi
t
Slave - word
address register
Data
register
7
WP
*2
A2
3
START
STOP
Control circuit
ACK
6
SCL
GND
4
＊
1
High voltage
generating circuit
7bit : BR24L01A-W
8bit : BR24L02-W
9bit : BR24L04-W
10bit : BR24L08-W
11bit : BR24L16-W
12bit : BR24L32-W
13bit : BR24L64-W
Power source
voltage detection
＊
5
: BR24L04-W
: BR24L08-W
: BR24L16-W
SDA
2
A0=N.C.
A0, A1=N.C.
A0, A1= N.C. A2=Don’t Use
Fig.2
Block diagram
●Pin
assignment and description
A0
A1
A2
GND
1
2
3
4
BR24L01A-W
BR24L02-W
BR24L04-W
BR24L08-W
BR24L16-W
BR24L32-W
BR24L64-W
8
7
6
5
Vcc
WP
SCL
SDA
Terminal
name
A0
A1
A2
GND
SDA
SCL
WP
Vcc
Input /
output
Input
Input
Input
-
Input /
output
Input
Input
-
Function
BR24L01A-W
BR24L02-W
BR24L04-W
BR24L08-W
BR24L16-W
BR24L32-W
BR24L64-W
Slave address setting
Slave address setting
Slave address setting
Reference voltage of all input / output, 0V
Not connected
Not connected
Not used
Slave address setting
Slave address setting
Slave address setting
Slave and word address, Serial data input serial data output
Serial clock input
Write protect terminal
Connect the power source.
4/32
●Characteristic
data (The following values are
6
Typ. ones.)
6
5
4
VIH1,2[V]
3
2
1
0
0
1
3
4
5
Vcc[V]
Fig.3 H input voltage VIH1,2
2
6
SPEC
1
0.8
5
4
VIL1,2[V]
3
2
1
0
0
3
4
5
6
Vcc[V]
Fig.4 L input voltageVIL1,2 (SCL,SDA,WP)
1
2
SPEC
Ta=85℃
Ta=-40℃
Ta=25℃
VOL1[V]
0.6
SPEC
Ta=85℃
Ta=25℃
0.4
0.2
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=-40℃
0
0
3
4
5
6
IOL1[mA]
Fig.5 L output voltage VOL1-IOL1 (VCC=2.5V)
1
2
1
0.8
0.6
VOL2[V]
ILI[μA]
Ta=85℃
Ta=25℃
1.2
SPEC
1.2
SPEC
1
0.8
ILO[μA]
0.6
0.4
0.2
6
0
0
1
2
3
Vcc[V]
4
5
6
Ta=85℃
Ta=25℃
Ta=-40℃
1
0.8
0.6
0.4
0.2
0
0
1
2
3
Vcc[V]
4
5
6
Ta=85℃
Ta=25℃
Ta=-40℃
0.4
SPEC
0.2
Ta=-40℃
0
0
1
2
3
4
IOL2[mA]
5
Fig.6 L output voltage VOL2-IOL2 (VCC=1.8V)
Fig.7 Input leak current ILI (SCL,WP)
3.5
0.6
[BR24L32/64 series]
Fig.8 Output leak current ILO(SDA)
2.5
[BR24L01/02/04/08/16 series]
[BR24L01A/02/04/08/16 series]
SPEC
2
ICC1[mA]
1.5
1
0.5
0
0
3
2.5
ICC1[mA]
2
1.5
1
0.5
0
0
fSCL=400kHz
DATA=AAh
SPEC
fSCL=400kHz
DATA=AAh
SPEC
0.5
ICC2[mA]
0.4
0.3
0.2
0.1
0
fSCL=400kHz
DATA=AAh
Ta=85℃
Ta=25℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=-40℃
3
4
5
6
Vcc[V]
Fig.9 Current consumption at WRITE action ICC1
(fscl=400kHz)
3.5
[BR24L01/02/04/08/16 series]
[BR24L01A/02/04/08/16 series]
1
2
1
2
3
Vcc[V]
4
5
6
0
Fig.10 Current consumption at WRITE action ICC1
(fSCL=400kHz)
0.6
[BR24L32/64 series]
3
4
5
6
Vcc[V]
Fig.11 Current consumption at READ action ICC2
(fSCL=400kHz)
SPEC
1
2
2.5
2
ICC1[mA]
1.5
1
0.5
0
0
1
2
3
Vcc[V]
4
5
6
Ta=25℃
Ta=85℃
Ta=-40℃
3
2.5
ICC1[mA]
2
1.5
1
0.5
0
0
1
2
3
Vcc[V]
4
5
6
Ta=25℃
Ta=85℃
Ta=-40℃
fSCL=100kHz
DATA=AAh
SPEC
0.5
ICC2[mA]
0.4
0.3
0.2
Ta=25℃
Ta=85℃
fSCL=100kHz
DATA=AAh
fSCL=100kHz
DATA=AAh
SPEC
0.1
0
0
Ta=-40℃
Fig.12 Current consumption at WRITE action ICC1
(fSCL=100kHz)
2.5
SPEC
Fig.13 Current consumption at WRITE action ICC1
(fSCL=100kHz)
10000
5
3
4
5
6
Vcc[V]
Fig.14 Current consumption at READ action ICC2
(fSCL=100kHz)
SPEC2
1
2
2
ISB[μA]
1.5
1
0.5
0
0
1
2
3
Vcc[V]
4
5
6
Ta=85℃
Ta=-40℃
Ta=25℃
1000
fSCL[kHz]
4
tHIGH [μs]
Ta=85℃
Ta=25℃
Ta=-40℃
SPEC1
SPEC2
3
2
1
0
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC1
100
10
1
0
1
2
3
Vcc[V]
4
5
6
0
1
2
3
Vcc[V]
4
5
6
Fig.15 Standby current ISB
5
SPEC2
Fig.16 SCL frequency fSCL
5
SPEC2
Fig.17 Data clock "H" time tHIGH
6
5
tSU:STA[μs]
4
3
2
1
0
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC1
SPEC2
4
tHD:STA[μs]
tLOW[μs]
3
2
1
0
0
3
4
5
Vcc[V]
Fig.18 Data clock "L" time tLOW
1
2
6
Ta=85℃
Ta=25℃
Ta=-40℃
SPEC1
4
3
2
1
0
0
1
2
3
Vcc[V]
4
5
6
Ta=85℃
Ta=25℃
Ta=-40℃
SPEC1
0
1
2
3
Vcc[V]
4
5
6
Fig.19 Start condition hold time tHD:STA
Fig.20 Start condition setup time tSU:STA
5/32
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