74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
Rev. 12 — 2 April 2013
Product data sheet
1. General description
The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D)
inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q
outputs.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing damaging backflow current through the device
when it is powered down.
The set and reset are asynchronous active LOW inputs and operate independently of the
clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time
prior to the LOW-to-HIGH clock transition for predictable operation.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and
fall times.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
24
mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LVC1G74DP
74LVC1G74DC
74LVC1G74GT
74LVC1G74GF
74LVC1G74GD
74LVC1G74GM
74LVC1G74GN
74LVC1G74GS
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
TSSOP8
VSSOP8
XSON8
XSON8
XSON8
XQFN8
XSON8
XSON8
Description
plastic thin shrink small outline package; 8 leads; body
width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
Version
SOT505-2
SOT765-1
Type number
plastic extremely thin small outline package; no leads; 8 SOT833-1
terminals; body 1
1.95
0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35
1
0.5 mm
plastic extremely thin small outline package; no leads;
8 terminals; body 3
2
0.5 mm
plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6
1.6
0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.2
1.0
0.35 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35
1.0
0.35 mm
SOT1089
SOT996-2
SOT902-2
SOT1116
SOT1203
4. Marking
Table 2.
Marking codes
Marking code
[1]
V74
V74
V74
Y4
V74
V74
Y4
Y4
Type number
74LVC1G74DP
74LVC1G74DC
74LVC1G74GT
74LVC1G74GF
74LVC1G74GD
74LVC1G74GM
74LVC1G74GN
74LVC1G74GS
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
74LVC1G74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 12 — 2 April 2013
2 of 25
NXP Semiconductors
74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
5. Functional diagram
SD
D
CP
SD
D
CP
FF
Q
RD
RD
001aah757
001aah758
Q
Q
S
Q
C1
1D
R
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Q
C
C
C
C
D
C
RD
C
C
Q
C
SD
mna421
CP
C
C
Fig 3.
Logic diagram
74LVC1G74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 12 — 2 April 2013
3 of 25
NXP Semiconductors
74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
6. Pinning information
6.1 Pinning
74LVC1G74
CP
1
8
V
CC
D
2
7
SD
74LVC1G74
CP
D
Q
GND
1
2
3
4
001aab659
8
7
6
5
V
CC
SD
RD
Q
Q
3
6
RD
GND
4
5
Q
001aab658
Transparent top view
Fig 4.
Pin configuration SOT505-2 and SOT765-1
Fig 5.
Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
74LVC1G74
terminal 1
index area
SD
1
V
CC
8
7
CP
CP
D
Q
GND
1
2
8
7
V
CC
RD
SD
RD
Q
Q
3
4
5
Q
2
6
D
74LVC1G74
3
4
6
5
GND
001aaf641
001aah948
Transparent top view
Transparent top view
Fig 6.
Pin configuration SOT996-2
Fig 7.
Pin configuration SOT902-2
74LVC1G74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 12 — 2 April 2013
4 of 25
NXP Semiconductors
74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
SOT505-2, SOT765-1, SOT833-1, SOT1089, SOT902-2
SOT996-2, SOT1116 and SOT1203
CP
D
Q
GND
Q
RD
SD
V
CC
1
2
3
4
5
6
7
8
7
6
5
4
3
2
1
8
clock input (LOW-to-HIGH, edge-triggered)
data input
complement output
ground (0 V)
true output
asynchronous reset-direct input (active LOW)
asynchronous set-direct input (active LOW)
supply voltage
Description
7. Functional description
Table 4.
Input
SD
L
H
L
[1]
Function table for asynchronous operation
[1]
Output
RD
H
L
L
CP
X
X
X
D
X
X
X
Q
H
L
H
Q
L
H
H
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
Table 5.
Input
SD
H
H
[1]
Function table for synchronous operation
[1]
Output
RD
H
H
CP
D
L
H
Q
n+1
L
H
Q
n+1
H
L
H = HIGH voltage level;
L = LOW voltage level;
= LOW-to-HIGH CP transition;
Q
n+1
= state after the next LOW-to-HIGH CP transition.
74LVC1G74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 12 — 2 April 2013
5 of 25
TI Technology Forum
京公网安备 11010802033920号
EEWORLD
