74LVC1G74GM datasheet, PDF - EEWORLD Datasheet

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74LVC1G74GM: DescriptionSingle D-type flip-flop with set and reset; positive edge trigger; Categorylogic logic; File Size162KB，25 Pages; ManufacturerPhilips Semiconductors (NXP Semiconductors N.V.); Websitehttps://www.nxp.com/

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74LVC1G74GM Overview

Single D-type flip-flop with set and reset; positive edge trigger

74LVC1G74GM Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Philips Semiconductors (NXP Semiconductors N.V.)
package instruction	SON, SOLCC8,.08,20
Reach Compliance Code	unknow
JESD-30 code	R-PDSO-N8
JESD-609 code	e0
Logic integrated circuit type	D FLIP-FLOP
Maximum Frequency@Nom-Su	175000000 Hz
MaximumI(ol)	0.024 A
Number of functions	1
Number of terminals	8
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SON
Encapsulate equivalent code	SOLCC8,.08,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
power supply	3.3 V
Prop。Delay @ Nom-Su	5.9 ns
Certification status	Not Qualified
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	DUAL
Trigger type	POSITIVE EDGE

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74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

Rev. 10 — 2 December 2011

Product data sheet

1. General description

The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D)

inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q

outputs.

This device is fully specified for partial power-down applications using I

OFF

. The I

OFF

circuitry disables the output, preventing damaging backflow current through the device

when it is powered down.

The set and reset are asynchronous active LOW inputs and operate independently of the

clock input. Information on the data input is transferred to the Q output on the

LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time

prior to the LOW-to-HIGH clock transition for predictable operation.

Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and

fall times.

2. Features and benefits



Wide supply voltage range from 1.65 V to 5.5 V

5 V tolerant inputs for interfacing with 5 V logic

High noise immunity

Complies with JEDEC standard:



JESD8-7 (1.65 V to 1.95 V)



JESD8-5 (2.3 V to 2.7 V)



JESD8-B/JESD36 (2.7 V to 3.6 V)

ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-A exceeds 200 V

24

mA output drive (V

= 3.0 V)

CMOS low power consumption

Latch-up performance exceeds 250 mA

Direct interface with TTL levels

Inputs accept voltages up to 5 V

Multiple package options

Specified from

40 C

to +85

C

and

40 C

to +125

C



74LVC1G74GM Related Products

	74LVC1G74GM	74LVC1G74GF	74LVC1G74GN	74LVC1G74GS	74LVC1G74_11	74LVC1G74GD
Description	Single D-type flip-flop with set and reset; positive edge trigger	Single D-type flip-flop with set and reset; positive edge trigger	Single D-type flip-flop with set and reset; positive edge trigger	Single D-type flip-flop with set and reset; positive edge trigger	Single D-type flip-flop with set and reset; positive edge trigger	Single D-type flip-flop with set and reset; positive edge trigger

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