DS1706EPA datasheet, PDF - EEWORLD Datasheet

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DS1706EPA: Description1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP8, 0.300 INCH, PLASTIC, DIP-8; CategoryPower/power management The power supply circuit; File Size968KB，13 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/

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1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP8, 0.300 INCH, PLASTIC, DIP-8

DS1706EPA Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Rochester Electronics
Parts packaging code	DIP
package instruction	DIP,
Contacts	8
Reach Compliance Code	unknown
Other features	PUSHBUTTON RESET OPTION
Adjustable threshold	NO
Analog Integrated Circuits - Other Types	POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 code	R-PDIP-T8
JESD-609 code	e0
length	9.375 mm
Humidity sensitivity level	1
Number of channels	1
Number of functions	1
Number of terminals	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	240
Maximum seat height	4.572 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	1.2 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	20
width	7.62 mm

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DS1705/DS1706

the reset to an active state. When V

returns to an in-tolerance condition, the reset signal is kept in the

active state for a minimum of 130 ms to allow the power supply and processor to stabilize.

The second function the DS1705/DS1706 performs is pushbutton reset control. The DS1705/DS1706

debounces the pushbutton input and guarantees an active reset pulse width of 130 ms minimum.

The third function is a watchdog timer. The DS1705/DS1706 has an internal timer that forces the

WDS

output signal to the active state if the strobe input is not driven low prior to time-out.

OPERATION

Power Monitor

The DS1705/DS1706 detects out-of-tolerance power supply conditions and warns a processor-based

system of impending power failure. When V

falls below the minimum V

tolerance, a comparator

outputs the

RST

(or RST) signal.

RST

(or RST) is an excellent control signal for a microprocessor, as

processing is stopped at the last possible moment of valid V

. On power-up,

RST

(or RST) are kept

active for a minimum of 130 ms to allow the power supply and processor to stabilize.

Pushbutton Reset

The DS1705/DS1706 provides an input pin for direct connection to a pushbutton reset (see Figure 2). The

pushbutton reset input requires an active low signal. Internally, this input is debounced and timed such

that a

RST

(or RST) signal of at least 130 ms minimum will be generated. The 130 ms delay commences

as the pushbutton reset input is released from the low level. The pushbutton can be initiated by connecting

the

WDS

NMI

outputs to the

PBRST

input as shown in Figure 3.

Non-Maskable Interrupt

The DS1705/DS1706 generates a non-maskable interrupt (

NMI

) for early warning of a power failure. A

precision comparator monitors the voltage level at the IN pin relative to an on-chip reference generated

by an internal band gap. The IN pin is a high impedance input allowing for a user-defined sense point. An

external resistor voltage divider network (Figure 5) is used to interface with high voltage signals. This

sense point may be derived from a regulated supply or from a higher DC voltage level closer to the main

system power input. Since the IN trip point V

is 1.25 volts, the proper values for R1 and R2 can be

determined by the equation as shown in Figure 5. Proper operation of the DS1705/DS1706 requires that

the voltage at the IN pin be limited to V

. Therefore, the maximum allowable voltage at the supply being

monitored (V

MAX

) can also be derived as shown in Figure 5. A simple approach to solving the equation is

to select a value for R2 high enough to keep power consumption low, and solve for R1. The flexibility of

the IN input pin allows for detection of power loss at the earliest point in a power supply system,

maximizing the amount of time for system shutdown between

NMI

and

RST

(or RST).

When the supply being monitored decays to the voltage sense point, the DS1705/DS1706 pulses the

NMI

output to the active state for a minimum 200

s.

The

NMI

power-fail detection circuitry also has built-in

hysteresis of 100

V.

The supply must be below the voltage sense point for approximately 5

s

before a

low

NMI

will be generated. In this way, power supply noise is removed from the monitoring function,

preventing false interrupts. During a power-up, any detected IN pin levels below V

by the comparator

are disabled from generating an interrupt until V

rises to V

CCTP

. As a result, any potential

NMI

pulse

will not be initiated until V

reaches V

CCTP

Connecting

NMI

PBRST

would allow non-maskable interrupt to generate an automatic reset when an

out-of-tolerance condition occurred in a monitored supply. An example is shown in Figure 3.

2 of 12

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