DS1707EPA datasheet, PDF - EEWORLD Datasheet

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DS1707EPA: Description1-CHANNEL POWER SUPPLY SUPPORT CKT, PDIP8, 0.300 INCH, PLASTIC, DIP-8; CategoryPower/power management The power supply circuit; File Size933KB，13 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/

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1-CHANNEL POWER SUPPLY SUPPORT CKT, PDIP8, 0.300 INCH, PLASTIC, DIP-8

DS1707EPA Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Rochester Electronics
Parts packaging code	DIP
package instruction	0.300 INCH, PLASTIC, DIP-8
Contacts	8
Reach Compliance Code	unknown
Other features	PUSHBUTTON RESET OPTION
Adjustable threshold	NO
Analog Integrated Circuits - Other Types	POWER SUPPLY SUPPORT CIRCUIT
JESD-30 code	R-PDIP-T8
JESD-609 code	e0
length	9.375 mm
Humidity sensitivity level	1
Number of channels	1
Number of functions	1
Number of terminals	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	240
Certification status	COMMERCIAL
Maximum seat height	4.572 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	1.2 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	20
width	7.62 mm

DS1707EPA Preview

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DS1707/DS1708

3.3 and 5.0-Volt MicroMonitor

www.maxim-ic.com

FEATURES

Holds microprocessor in check during power

transients

Automatically restarts microprocessor after

power failure

Monitors pushbutton for external override

Accurate 5%, 10% or 20% resets for 3.3V

systems and 5% or 10% resets for 5.0V

systems

Eliminates the need for discrete components

20% tolerance compatible with 3.0V systems

Pin compatible with the MAXIM

MAX707/MAX708 in 8-pin DIP, 8-pin SOIC

packages

8-pin DIP, 8-pin and

m-SOP

SOIC and 8-pin

m-SOP

packages available

Industrial temperature range -40°C to +85°C

PIN ASSIGNMENT

PBRST

GND

RST

NMI

8-Pin DIP (300-mil)

PBRST

GND

RST

NMI

8-Pin SOIC (150-mil)

RST

PBRST

NMI

GND

8-Pin

m-SOP

(118-mil)

See Mech. Drawings Section on website

DS1707 and DS1708_R/S/T

PIN DESCRIPTION

PBRST

GND

NMI

RST

- Pushbutton Reset Input

- Power Supply

- Ground

- Input

- Non-maskable Interrupt

- No Connect

- Active Low Reset Output

- Active High Reset Output

DESCRIPTION

The DS1707/DS1708 3.3- or 5.0-Volt MicroMonitor monitors three vital conditions for a microprocessor:

power supply, voltage sense, and external override. A precision temperature-compensated reference and

comparator circuit monitor the status of V

at the device and at an upstream point for maximum

protection. When the sense input detects an out-of-tolerance condition a non-maskable interrupt is

generated. As the voltage at the device degrades an internal power fail signal is generated which forces

the reset to an active state. When V

returns to an in-tolerance condition, the reset signal is kept in the

active state for a minimum of 130 ms to allow the power supply and processor to stabilize.

1 of 10

041305

DS1707/DS1708

The third function the DS1707/DS1708 performs is pushbutton reset control. The DS1707/DS1708

debounces the pushbutton input and guarantees an active reset pulse width of 130 ms minimum.

OPERATION

Power Monitor

The DS1707/DS1708 detects out-of-tolerance power supply conditions and warns a processor-based

system of impending power failure. When V

falls below the minimum V

tolerance, a comparator

outputs the RST and

RST

signals. RST and

RST

are excellent control signals for a microprocessor, as

processing is stopped at the last possible moment of valid V

. On power-up, RST and

RST

are kept

active for a minimum of 130 ms to allow the power supply and processor to stabilize.

Pushbutton Reset

The DS1707/DS1708 provides an input pin for direct connection to a pushbutton reset (see Figure 2). The

pushbutton reset input requires an active low signal. Internally, this input is debounced and timed such

that RST and

RST

signals of at least 130 ms minimum will be generated. The 130 ms delay commences

as the pushbutton reset input is released from the low level. The pushbutton can be initiated by connecting

the

NMI

output to the

PBRST

input as shown in Figure 3.

Non-Maskable Interrupt

The DS1707/DS1708 generates a non-maskable interrupt (

NMI

) for early warning of a power failure. A

precision comparator monitors the voltage level at the IN pin relative to an on-chip reference generated

by an internal band gap. The IN pin is a high impedance input allowing for a user-defined sense point. An

external resistor voltage divider network (Figure 5) is used to interface with high voltage signals. This

sense point may be derived from a regulated supply or from a higher DC voltage level closer to the main

system power input. Since the IN trip point V

is 1.25 volts, the proper values for R1 and R2 can be

determined by the equation as shown in Figure 5. Proper operation of the DS1707/DS1708 requires that

the voltage at the IN pin be limited to V

. Therefore, the maximum allowable voltage at the supply being

monitored (V

MAX

) can also be derived as shown in Figure 5. A simple approach to solving the equation is

to select a value for R2 high enough to keep power consumption low, and solve for R1. The flexibility of

the IN input pin allows for detection of power loss at the earliest point in a power supply system,

maximizing the amount of time for system shut-down between

NMI

and RST/

RST

When the supply being monitored decays to the voltage sense point, the DS1707/DS1708 pulses the

NMI

output to the active state for a minimum 200

ms.

The

NMI

power-fail detection circuitry also has built-in

hysteresis of 100

mV.

The supply must be below the voltage sense point for approximately 5

before a

low

NMI

will be generated. In this way, power supply noise is removed from the monitoring function,

preventing false interrupts. During a power-up, any detected IN pin levels below V

by the comparator

are disabled from generating an interrupt until V

rises to V

CCTP

. As a result, any potential

NMI

pulse

will not be initiated until V

reaches V

CCTP

Connecting

NMI

PBRST

would allow the non-maskable interrupt to generate an automatic reset when

an out-of-tolerance condition occurred in a monitored supply. An example is shown in Figure 3.

2 of 10

DS1707/DS1708

MICROMONITOR BLOCK DIAGRAM

Figure 1

40kW

PUSHBUTTON RESET

Figure 2

PUSHBUTTON RESET CONTROLLED BY

NMI

Figure 3

3 of 10

DS1707/DS1708

TIMING DIAGRAM: PUSHBUTTON RESET

Figure 4

NON-MASKABLE INTERRUPT CIRCUIT EXAMPLE

Figure 5

SENSE

Example:

R1+ R2

X 1.25

MAX

SENSE

X V

SENSE

= 4.50V at the trip point

= 3.3V

10 kΩ = R2

4.50

X 3.3 = 11.88V maximum

1.25

Therefore:

4.50 =

10k

X 1.25

10k

R1 = 26 kΩ

4 of 10

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