ZBT SRAM, 256KX18, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
IDT71V2548S150PFI8 Parametric
Parameter Name
Attribute value
Is it Rohs certified?
incompatible
Maker
IDT (Integrated Device Technology)
Parts packaging code
QFP
package instruction
14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
Contacts
100
Reach Compliance Code
not_compliant
ECCN code
3A991.B.2.A
Maximum access time
3.8 ns
Other features
PIPELINED ARCHITECTURE
JESD-30 code
R-PQFP-G100
JESD-609 code
e0
length
20 mm
memory density
4718592 bit
Memory IC Type
ZBT SRAM
memory width
18
Humidity sensitivity level
3
Number of functions
1
Number of terminals
100
word count
262144 words
character code
256000
Operating mode
SYNCHRONOUS
Maximum operating temperature
85 °C
Minimum operating temperature
-40 °C
organize
256KX18
Package body material
PLASTIC/EPOXY
encapsulated code
LQFP
Package shape
RECTANGULAR
Package form
FLATPACK, LOW PROFILE
Parallel/Serial
PARALLEL
Peak Reflow Temperature (Celsius)
240
Certification status
Not Qualified
Maximum seat height
1.6 mm
Maximum supply voltage (Vsup)
3.465 V
Minimum supply voltage (Vsup)
3.135 V
Nominal supply voltage (Vsup)
3.3 V
surface mount
YES
technology
CMOS
Temperature level
INDUSTRIAL
Terminal surface
Tin/Lead (Sn85Pb15)
Terminal form
GULL WING
Terminal pitch
0.65 mm
Terminal location
QUAD
Maximum time at peak reflow temperature
20
width
14 mm
IDT71V2548S150PFI8 Preview
128K x 36, 256K x 18
3.3V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
x
x
IDT71V2546
IDT71V2548
Features
128K x 36, 256K x 18 memory configurations
Supports high performance system speed - 150 MHz
(3.8 ns Clock-to-Data Access)
ZBT
TM
Feature - No dead cycles between write and read
cycles
Internally synchronized output buffer enable eliminates the
need to control
OE
Single R/W (READ/WRITE) control pin
W
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW
1
-
BW
4
) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%)
2.5V I/O Supply (V
DDQ)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine
pitch ball grid array
cycle, and two cycles later the associated data cycle occurs, be it read
or write.
The IDT71V2546/48 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V2546/48 to
be suspended as long as necessary. All synchronous inputs are ignored
when (CEN) is high and the internal device registers will hold their previous
values.
There are three chip enable pins (CE
1
, CE
2
,
CE
2
) that allow the user
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state two cycles after chip is deselected or a write is
initiated.
The IDT71V2546/48 has an on-chip burst counter. In the burst mode,
the IDT71V2546/48 can provide four cycles of data for a single address
presented to the SRAM. The order of the burst sequence is defined by the
LBO
input pin. The
LBO
pin selects between linear and interleaved burst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
The IDT71V2546/48 SRAMs utilize IDT's latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array (fBGA).
x
x
x
x
x
x
x
x
x
x
Description
The IDT71V2546/48 are 3.3V high-speed 4,718,592-bit (4.5 Mega-
bit) synchronous SRAMS. They are designed to eliminate dead bus cycles
when turning the bus around between reads and writes, or writes and
reads. Thus, they have been given the name ZBT
TM
, or Zero Bus
Turnaround.
Address and control signals are applied to the SRAM during one clock
Pin Description Summary
A
0
-A
17
CE
1
, CE
2
,
CE
2
OE
R/W
CEN
BW
1
,
BW
2
,
BW
3
,
BW
4
CLK
ADV/LD
LBO
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
V
DD
, V
DDQ
V
SS
Address Inputs
Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Advance burst address / Load new address
Linear / Interleaved Burst Order
Data Input / Output
Core Power, I/O Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Synchronous
Static
Static
5294 tbl 01
ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
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