= 2.5 V. All specifications −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal to (Noise + Distortion) Ratio
1
Total Harmonic Distortion
1
Peak Harmonic or Spurious Noise
1
Intermodulation Distortion
1
Second-Order Terms
Third-Order Terms
Channel-to-Channel Isolation
1
DC ACCURACY
Resolution
Minimum Resolution for Which
No Missing Codes Are Guaranteed
Integral Nonlinearity (INL)
1
Differential Nonlinearity (DNL)
1
Gain Error
1
Gain Error Match
1
Offset Error
1
Offset Error Match
1
ANALOG INPUTS
2
V
DD
= 5 V ± 10%
V
IN1
to V
IN8
Input Voltage
V
MID
Input Voltage
V
DD
= 3 V ± 10%
V
IN1
to V
IN8
Input Voltage
V
MID
Input Voltage
V
IN
Input Leakage Current
V
IN
Input Capacitance
V
MID
Input Impedance
REFERENCE INPUT
V
REF IN/OUT
Input Voltage Range
Input Current
ON-CHIP REFERENCE
Reference Error
Temperature Coefficient
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN
Version B
48
−55
−55
−65
−65
−70
8
8
±0.75
±0.75
±2
±0.1
±1
±0.1
Unit
dB min
dB max
dB max
fa = 27.3 kHz, fb = 28.3 kHz
dB typ
dB typ
dB typ
Bits
Bits
LSB max
LSB max
LSB max
LSB typ
LSB max
LSB typ
See Analog Input section
Input voltage span = 2.5 V
V
DD
0
V
DD
− 1.25
1.25
V
DD
0
V
DD
− 1
1
±1
15
6
2.55
2.45
1
100
±50
50
2.4
0.8
2
0.4
±1
10
V max
V min
V max
V min
V max
V min
V max
V min
μA max
pF max
kΩ typ
V max
V min
μA typ
μA max
mV max
ppm/°C typ
V min
V max
V min
V max
μA max
pF max
V
DD
= 5 V ± 10%
V
DD
= 5 V ± 10%
V
DD
= 3 V ± 10%
V
DD
= 3 V ± 10%
10 nA typical, V
IN
= 0 V to V
DD
Test Condition/Comment
f
IN
= 30 kHz, f
SAMPLE
= 2 MHz
f
IN
= 20 kHz
Default V
MID
= 1.25 V
Input voltage span = 2 V
Default V
MID
= 1 V
2.5 V + 2%
2.5 V − 2%
Nominal 2.5 V
Rev. C | Page 3 of 28
AD7822/AD7825/AD7829
Parameter
LOGIC OUTPUTS
Output High Voltage, V
OH
Version B
Unit
Test Condition/Comment
I
SOURCE
= 200 μA
V
DD
= 5 V ± 10%
V
DD
= 3 V ± 10%
I
SINK
= 200 μA
V
DD
= 5 V ± 10%
V
DD
= 3 V ± 10%
4
2.4
Output Low Voltage, V
OL
0.4
0.2
±1
10
200
420
±1
4.5
5.5
2.7
3.3
12
5
0.2
36
9.58
23.94
V min
V min
V max
V max
μA max
pF max
ns max
ns max
LSB max
V min
V max
V min
V max
mA max
μA max
μA typ
mW max
mW typ
mW typ
High Impedance Leakage Current
High Impedance Capacitance
CONVERSION RATE
Track-and-Hold Acquisition Time
Conversion Time
POWER SUPPLY REJECTION
V
DD
± 10%
POWER REQUIREMENTS
V
DD
V
DD
I
DD
Normal Operation
Power-Down
Power Dissipation
Normal Operation
Power-Down
200 kSPS
500 kSPS
1
2
See Circuit Description section
5 V ± 10%; for specified performance
3 V ± 10%; for specified performance
8 mA typical
Logic inputs = 0 V or V
DD
V
DD
= 3 V
24 mW typical
See the Terminology section of this data sheet.
Refer to the Analog Input section for an explanation of the analog input(s).
Rev. C | Page 4 of 28
AD7822/AD7825/AD7829
TIMING CHARACTERISTICS
V
REF IN/OUT
= 2.5 V. All specifications −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
1,
2
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9 3
t
10 4
t
11
t
12
t
13
t
POWER UP
t
POWER UP
1
2
5 V
±
10%
420
20
30
110
70
10
0
0
30
10
5
20
10
15
200
25
1
3 V
±
10%
420
20
30
110
70
10
0
0
30
20
5
20
10
15
200
25
1
Unit
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
μs typ
μs max
Conditions/Comments
Conversion time
Minimum CONVST pulse width
Minimum time between the rising edge of RD and the next falling edge of convert star
EOC pulse width
RD rising edge to EOC pulse high
CS to RD setup time
CS to RD hold time
Minimum RD pulse width
Data access time after RD low
Bus relinquish time after RD high
Address setup time before falling edge of RD
Address hold time after falling edge of RD
Minimum time between new channel selection and convert start
Power-up time from rising edge of CONVST using on-chip reference
Power-up time from rising edge of CONVST using external 2.5 V reference
Sample tested to ensure compliance.
See Figure 24, Figure 25, and Figure 26.
3
Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V with V
DD
= 5 V ± 10%, and time required for an output
to cross 0.4 V or 2.0 V with V
DD
= 3 V ± 10%.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
10
, quoted in the timing characteristics is the true bus relinquish time
of the part and, as such, is independent of external bus loading capacitances.
TIMING DIAGRAM
200µA
I
OL
TO OUTPUT
PIN
2.1V
C
L
50pF
200µA
I
OH
01321-002
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
京公网安备 11010802033920号
EEWORLD
