GS81302D37E-375T datasheet, PDF

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GS81302D37E-375T: DescriptionDDR SRAM, 4MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165; Categorystorage storage; File Size845KB，30 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS81302D37E-375T Overview

DDR SRAM, 4MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165

GS81302D37E-375T Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	GSI Technology
Parts packaging code	BGA
package instruction	15 X 17 MM, 1 MM PITCH, FPBGA-165
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
length	17 mm
memory density	150994944 bit
Memory IC Type	DDR SRAM
memory width	36
Number of functions	1
Number of terminals	165
word count	4194304 words
character code	4000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4MX36
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm

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Preliminary

GS81302D19/37E-400/375

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• 2.0 Clock Latency

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 4 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD) Supporter

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

144Mb SigmaQuad-II+

Burst of 4 SRAM

400 MHz–375 MHz

1.8 V V

1.8 V and 1.5 V I/O

Bottom View

165-Bump, 15 mm x 17 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

SigmaQuad™ Family Overview

The GS81302D19/37E are built in compliance with the

SigmaQuad-II+ SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 150,994,944-bit (144Mb)

SRAMs. The GS81302D19/37E SigmaQuad SRAMs are just

one element in a family of low power, low voltage HSTL I/O

SRAMs designed to operate at the speeds needed to implement

economical high performance networking systems.

Clocking and Addressing Schemes

The GS81302D19/37E SigmaQuad-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Because Separate I/O SigmaQuad-II+ B4 RAMs always

transfer data in four packets, A0 and A1 are internally set to 0

for the first read or write transfer, and automatically

incremented by 1 for the next transfers.

Parameter Synopsis

-400

tKHKH

tKHQV

2.5ns

0.45 ns

-375

2.67 ns

0.45 ns

Rev: 1.00a 4/2008

1/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS81302D19/37E-400/375

Background

Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are

needed. Therefore, the SigmaQuad-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O

SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from

Separate I/O SRAMs can cut the RAM’s bandwidth in half.

Alternating Read-Write Operations

SigmaQuad-II SRAMs follow a few simple rules of operation.

- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.

- Read or Write data transfers in progress may not be interrupted and re-started.

- R and W high always deselects the RAM.

- All address, data, and control inputs are sampled on clock edges.

In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for

details.

SigmaQuad-II+ B4 SRAM DDR Read

The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on

the Read Enable-bar pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. .

Clocking in a high on the Read Enable-bar pin, R, begins a read port deselect cycle.

SigmaQuad-II+ B4 SRAM DDR Write

The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on

the Write Enable-bar pin, W, and a high on the Read Enable-bar pin, R, begins a write cycle. W is always ignored if the previous

command was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge

of K, and finally by the next rising edge of K. and by the rising edge of the K that follows.

Rev: 1.00a 4/2008

5/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS81302D37E-375T Related Products

	GS81302D37E-375T	GS81302D37E-375	GS81302D19GE-400T	GS81302D19GE-375T	GS81302D19GE-375
Description	DDR SRAM, 4MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165	DDR SRAM, 4MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165	DDR SRAM, 8MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165	DDR SRAM, 8MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165	DDR SRAM, 8MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
Is it lead-free?	Contains lead	Contains lead	Lead free	Lead free	Lead free
Is it Rohs certified?	incompatible	incompatible	conform to	conform to	conform to
Parts packaging code	BGA	BGA	BGA	BGA	BGA
package instruction	15 X 17 MM, 1 MM PITCH, FPBGA-165	BGA,	BGA,	15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165	BGA,
Contacts	165	165	165	165	165
Reach Compliance Code	compliant	compliant	compliant	compliant	compli
ECCN code	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B
Maximum access time	0.45 ns	0.45 ns	0.45 ns	0.45 ns	0.45 ns
Other features	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165
length	17 mm	17 mm	17 mm	17 mm	17 mm
memory density	150994944 bit	150994944 bit	150994944 bit	150994944 bit	150994944 bi
Memory IC Type	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM
memory width	36	36	18	18	18
Number of functions	1	1	1	1	1
Number of terminals	165	165	165	165	165
word count	4194304 words	4194304 words	8388608 words	8388608 words	8388608 words
character code	4000000	4000000	8000000	8000000	8000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C
organize	4MX36	4MX36	8MX18	8MX18	8MX18
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA	BGA	BGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	260	260	260
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum supply voltage (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	15 mm	15 mm	15 mm	15 mm	15 mm
Maker	GSI Technology	-	GSI Technology	GSI Technology	GSI Technology
JESD-609 code	-	-	e1	e1	e1
Humidity sensitivity level	-	-	3	3	3
Terminal surface	-	-	Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)

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