ADVANCE INFORMATION
Am29BDS640G
64 Megabit (4 M x 16-Bit)
CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■
Single 1.8 volt read, program and erase (1.65 to 1.95
volt)
■
Manufactured on 0.17 µm process technology
■
Enhanced VersatileIO™ (V
IO
) Feature
— Device generates data output voltages and tolerates
data input voltages as determined by the voltage on
the V
IO
pin
— 1.8V and 3V compatible I/O signals
■
Simultaneous Read/Write operation
— Data can be continuously read from one bank while
executing erase/program functions in other bank
— Zero latency between read and write operations
— Four bank architecture: 16Mb/16Mb/16Mb/16Mb
■
Programmable Burst Interface
— 2 Modes of Burst Read Operation
— Linear Burst: 8, 16, and 32 words with wrap-around
— Continuous Sequential Burst
■
Sector Architecture
— Eight 8 Kword sectors and one hundred twenty-six 32
Kword sectors
— Banks A and D each contain four 8 Kword sectors
and thirty-one 32 Kword sectors; Banks B and C
each contain thirty-two 32 Kword sectors
— Eight 8 Kword boot sectors, four at the top of the
address range, and four at the bottom of the address
range
■
Minimum 1 million erase cycle guarantee per sector
■
20-year data retention at 125°C
— Reliable operation for the life of the system
■
80-ball FBGA package
■
Power dissipation (typical values, C
L
= 30 pF)
— Burst Mode Read: 10 mA
— Simultaneous Operation: 25 mA
— Program/Erase: 15 mA
— Standby mode: 0.2 µA
HARDWARE FEATURES
■
Sector Protection
— Software command sector locking
■
Handshaking feature available
— Provides host system with minimum possible latency
by monitoring RDY
■
Hardware reset input (RESET#)
— Hardware method to reset the device for reading array
data
■
WP# input
— Write protect (WP#) function protects sectors 0 and 1
(bottom boot), or sectors 132 and 133 (top boot),
regardless of sector protect status
■
ACC input: Acceleration function reduces
programming time; all sectors locked when ACC = V
IL
■
CMOS compatible inputs, CMOS compatible outputs
■
Low V
CC
write inhibit
SOFTWARE FEATURES
■
Supports Common Flash Memory Interface (CFI)
■
Software command set compatible with JEDEC 42.4
standards
— Backwards compatible with Am29F and Am29LV
families
■
Data# Polling and toggle bits
— Provides a software method of detecting program
and erase operation completion
■
Erase Suspend/Resume
— Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation
■
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
PERFORMANCE CHARCTERISTICS
■
Read access times at 54/40 MHz
— Burst access times of 13.5/20 ns @ 30 pF at
industrial temperature range
— Asynchronous random access times of 70 ns (at 30
pF)
— Synchronous latency of 87.5/95 ns with 1.8 V V
IO
, and
88.0/95 ns with 3.0 V V
IO
(at 30 pF)
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication#
25903
Rev:
A
Amendment+4
Issue Date:
July 26, 2002
Refer to AMD’s Website (www.amd.com) for the latest information.
A D V A N C E
I N F O R M A T I O N
GENERAL DESCRIPTION
The Am29BDS640G is a 64 Mbit, 1.8 Volt-only, simulta-
neous Read/Write, Burst Mode Flash memory device, orga-
nized as 4,194,304 words of 16 bits each. This device uses
a single V
CC
of 1.65 to 1.95 V to read, program, and erase
the memory array. The device supports Enhanced V
IO
to
offer up to 3V compatible inputs and outputs. A 12.0-volt V
ID
may be used for faster program performance if desired. The
device can also be programmed in standard EPROM pro-
grammers.
At 54 MHz, the device provides a burst access of 13.5 ns at
30 pF with a latency of 87.5 ns at 30 pF. At 40 MHz, the de-
vice provides a burst access of 20 ns at 30 pF with a latency
of 95 ns at 30 pF. The device operates within the industrial
temperature range of -40°C to +85°C. The device is offered
in the 80-ball FBGA package.
The Simultaneous Read/Write architecture provides
simul-
taneous operation
by dividing the memory space into four
banks. The device can improve overall system performance
by allowing a host system to program or erase in one bank,
then immediately and simultaneously read from another
bank, with zero latency. This releases the system from wait-
ing for the completion of program or erase operations.
The device is divided as shown in the following table:
Bank
A
31
B
C
D
4
8 Kwords
32
32
31
32 Kwords
32 Kwords
32 Kwords
32 Kwords
Quantity
4
Size
8 Kwords
The clock polarity feature provides system designers a
choice of active clock edges, either rising or falling. The ac-
tive clock edge initiates burst accesses and determines
when data will be output.
The device is entirely command set compatible with the
JEDEC 42.4 single-power-supply Flash standard.
Com-
mands are written to the command register using standard
microprocessor write timing. Register contents serve as in-
puts to an internal state-machine that controls the erase and
programming circuitry. Write cycles also internally latch ad-
dresses and data needed for the programming and erase
operations. Reading data out of the device is similar to read-
ing from other Flash or EPROM devices.
The
Erase Suspend/Erase Resume
feature enables the
user to put erase on hold for any period of time to read data
from, or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation in
progress and resets the internal state machine to reading
array data. The RESET# pin may be tied to the system reset
circuitry. A system reset would thus also reset the device,
enabling the system microprocessor to read boot-up firm-
ware from the Flash memory device.
The host system can detect whether a program or erase op-
eration is complete by using the device status bit DQ7
(Data# Polling) and DQ6/DQ2 (toggle bits). After a program
or erase cycle has been completed, the device automatically
returns to reading array data.
The
sector erase architecture
allows memory sectors to be
erased and reprogrammed without affecting the data con-
tents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection
measures include a low V
CC
de-
tector that automatically inhibits write operations during
power transitions. The device also offers two types of data
protection at the sector level. The
sector lock/unlock com-
mand sequence
disables or re-enables both program and
erase operations in any sector. When at V
IL
,
WP#
locks sec-
tors 0 and 1 (bottom boot device) or sectors 132 and 133
(top boot device).
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of time, the
device enters the
automatic sleep mode.
The system can
also place the device into the
standby mode.
Power con-
sumption is greatly reduced in both modes.
AMD’s Flash technology combines years of Flash memory
manufacturing experience to produce the highest levels of
quality, reliability and cost effectiveness. The device electri-
cally erases all bits within a sector simultaneously via
Fowler-Nordheim tunnelling. The data is programmed using
hot electron injection.
The Enhanced VersatileIO™ (V
IO
) control allows the host
system to set the voltage levels that the device generates at
its data outputs and the voltages tolerated at its data inputs
to the same voltage level that is asserted on the V
IO
pin.
This allows the device to operate in 1.8 V and 3 V system
environments as required.
The device uses Chip Enable (CE#), Write Enable (WE#),
Address Valid (AVD#) and Output Enable (OE#) to control
asynchronous read and write operations. For burst opera-
tions, the device additionally requires Ready (RDY), and
Clock (CLK). This implementation allows easy interface with
minimal glue logic to a wide range of microprocessors/micro-
controllers for high performance read operations.
The burst read mode feature gives system designers flexibil-
ity in the interface to the device. The user can preset the
burst length and wrap through the same memory space, or
read the flash array in continuous mode.
2
Am29BDS640G
May 9, 2002
A D V A N C E
I N F O R M A T I O N
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram of Simultaneous
Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Special Handling Instructions for FBGA Package .................... 7
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Table 1. Device Bus Operations ....................................................10
Sector Lock/Unlock Command Sequence .............................. 23
Reset Command ..................................................................... 23
Autoselect Command Sequence ............................................ 24
Program Command Sequence ............................................... 24
Unlock Bypass Command Sequence ..................................... 24
Figure 2. Erase Operation.............................................................. 25
Chip Erase Command Sequence ........................................... 25
Sector Erase Command Sequence ........................................ 26
Erase Suspend/Erase Resume Commands ........................... 26
Figure 3. Program Operation ......................................................... 27
Command Definitions ............................................................. 28
Table 13. Command Definitions .................................................... 28
Enhanced VersatileIO™ (V
IO
) Control .................................... 10
Requirements for Asynchronous Read
Operation (Non-Burst) ............................................................ 10
Requirements for Synchronous (Burst) Read Operation ........ 11
8-, 16-, and 32-Word Linear Burst with Wrap Around ............ 11
Table 2. Burst Address Groups .......................................................11
Write Operation Status . . . . . . . . . . . . . . . . . . . . 29
DQ7: Data# Polling ................................................................. 29
Figure 4. Data# Polling Algorithm .................................................. 29
RDY: Ready ............................................................................ 30
DQ6: Toggle Bit I .................................................................... 30
Figure 5. Toggle Bit Algorithm........................................................ 30
Burst Mode Configuration Register ........................................ 11
Handshaking Option ............................................................... 12
Simultaneous Read/Write Operations with Zero Latency ....... 12
Writing Commands/Command Sequences ............................ 12
Accelerated Program Operation ............................................. 12
Autoselect Functions .............................................................. 12
Standby Mode ........................................................................ 13
Automatic Sleep Mode ........................................................... 13
RESET#: Hardware Reset Input ............................................. 13
Output Disable Mode .............................................................. 13
Hardware Data Protection ...................................................... 13
Write Protect (WP#) ................................................................ 13
Low V
CC
Write Inhibit .............................................................. 13
Write Pulse “Glitch” Protection ............................................... 14
Logical Inhibit .......................................................................... 14
Power-Up Write Inhibit ............................................................ 14
VCC and VIO Power-up And Power-down Sequencing ......... 14
Common Flash Memory Interface (CFI) . . . . . . . 14
Table 3. CFI Query Identification String ..........................................14
Table 4. System Interface String .....................................................15
Table 5. Device Geometry Definition ..............................................15
Table 6. Primary Vendor-Specific Extended Query ........................16
Table 7. Sector Address Table ........................................................17
DQ2: Toggle Bit II ................................................................... 30
Table 14. DQ6 and DQ2 Indications .............................................. 31
Reading Toggle Bits DQ6/DQ2 ............................................... 31
DQ5: Exceeded Timing Limits ................................................ 31
DQ3: Sector Erase Timer ....................................................... 32
Table 15. Write Operation Status ................................................... 32
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 33
Figure 6. Maximum Negative Overshoot Waveform ...................... 33
Figure 7. Maximum Positive Overshoot Waveform........................ 33
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 33
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 8. Test Setup....................................................................... 35
Table 16. Test Specifications ......................................................... 35
Key to Switching Waveforms. . . . . . . . . . . . . . . . 35
Switching Waveforms. . . . . . . . . . . . . . . . . . . . . . 35
Figure 9. Input Waveforms and Measurement Levels ................... 35
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36
VCC and VIO Power-up .......................................................... 36
Figure 10. V
CC
and V
IO
Power-up Diagram ................................... 36
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
Synchronous/Burst Read ........................................................ 37
Figure 11. CLK Synchronous Burst Mode Read
(rising active CLK)..........................................................................
Figure 12. CLK Synchronous Burst Mode Read
(Falling Active Clock) .....................................................................
Figure 13. Synchronous Burst Mode Read ....................................
Figure 14. 8-word Linear Burst with Wrap Around .........................
Figure 15. Burst with RDY Set One Cycle Before Data .................
Figure 16. Handshake Burst Mode Read
Starting at an Even Address ..........................................................
Figure 17. Handshake Burst Mode Read
Starting at an Odd Address............................................................
38
39
40
40
41
42
43
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 21
Reading Array Data ................................................................ 21
Set Burst Mode Configuration Register Command Sequence 21
Figure 1. Synchronous/Asynchronous State Diagram .................... 21
Read Mode Setting ................................................................. 21
Programmable Wait State Configuration ................................ 21
Table 8. Programmable Wait State Settings ...................................22
Handshaking Option ............................................................... 22
Table 9. Initial Access Cycles vs. Frequency ..................................22
Non-Handshaking Operation .................................................. 22
Table 10. Wait States for Non-Handshaking ...................................22
Asynchronous Read ............................................................... 44
Figure 18. Asynchronous Mode Read with Latched Addresses .... 44
Figure 19. Asynchronous Mode Read............................................ 45
Figure 20. Reset Timings............................................................... 46
Burst Read Mode Configuration ............................................. 22
Table 11. Burst Read Mode Settings ..............................................23
Burst Active Clock Edge Configuration ................................... 23
RDY Configuration .................................................................. 23
Configuration Register ............................................................ 23
Table 12. Burst Mode Configuration Register .................................23
Erase/Program Operations ..................................................... 47
Figure 21. Asynchronous Program Operation Timings .................. 48
Figure 22. Alternate Asynchronous Program Operation Timings... 49
Figure 23. Synchronous Program Operation Timings.................... 50
May 9, 2002
Am29BDS640G
3
A D V A N C E
I N F O R M A T I O N
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 9,
Initial Access Cycles vs. Frequency .......................... 62
Autoselect Command Sequence ............................................ 62
RDY: Ready ............................................................................ 62
DC Characteristics .................................................................. 62
Figure 21, Figure 23 ............................................................... 62
Figure 22, Figure 24 ............................................................... 62
Table 1, Device Bus Operations ............................................. 62
Writing Commands/Command Sequences ............................. 62
AC Characteristics .................................................................. 62
Figure 20, Asynchronous Program Operation Timings ........... 62
Figure 21, Alternate Asynchronous Program Operation Timings
62
Figure 22, Synchronous Program Operation Timings ............ 62
Figure 23, Alternate Synchronous Program Operation Timings .
62
Figure 24. Alternate Synchronous Program Operation Timings ..... 51
Figure 25. Chip/Sector Erase Command Sequence....................... 52
Figure 26. Accelerated Unlock Bypass Programming Timing......... 53
Figure 27. Data# Polling Timings (During Embedded Algorithm) ... 54
Figure 28. Toggle Bit Timings (During Embedded Algorithm)......... 54
Figure 29. Synchronous Data Polling Timings/Toggle Bit Timings . 55
Figure 30. Latency with Boundary Crossing ................................... 56
Figure 31. Latency with Boundary Crossing
into Program/Erase Bank ................................................................ 57
Figure 32. Example of Wait States Insertion
(Non-Handshaking Device) ............................................................. 58
Figure 33. Back-to-Back Read/Write Cycle Timings....................... 59
Erase and Programming Performance . . . . . . . . 60
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . . 61
FBE080—80-ball Fine-Pitch Ball Grid Array (FBGA) 11
x 12 mm Package .................................................................. 61
4
Am29BDS640G
May 9, 2002
A D V A N C E
I N F O R M A T I O N
PRODUCT SELECTOR GUIDE
Am29BDS640G
Part
Number
Synchronous/Burst
Speed/V
IO
/Handshaking
Option
Max Initial Access Time,
ns (t
IACC
)
Max Burst Access Time,
ns (t
BACC
)
Max OE# Access, ns (t
OE
)
98, 99,
78, 79
73, 74
93, 94
(54 MHz) (54 MHz)
(40 MHz)
95
20
20
87.5
13.5
13.5
88
14
14
Asynchronous
Speed/V
IO
/Handshaking
Option
Max Access Time,
ns (t
ACC
)
Max CE# Access,
ns (t
CE
)
Max OE# Access, ns (t
OE
)
78, 79,
73, 74
70
70
20
98, 99,
93, 94
90
90
20.5
V
CC
=
1.65 –
1.95 V
BLOCK DIAGRAM
V
CC
V
SS
V
SSIO
V
IO
RDY
Buffer
RDY
Erase Voltage
Generator
WE#
RESET#
WP#
ACC
State
Control
Command
Register
Input/Output
Buffers
DQ15–DQ0
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
Data
Latch
CE#
OE#
Y-Decoder
Timer
Address Latch
V
CC
Detector
Y-Gating
X-Decoder
Cell Matrix
AVD#
CLK
Burst
State
Control
Burst
Address
Counter
A21–A0
May 9, 2002
Am29BDS640G
5
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