AMS73CAG02808RAUJH7E datasheet, PDF

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AMS73CAG02808RAUJH7E: DescriptionHIGH PERFORMANCE 1Gbit DDR3 SDRAM; File Size672KB，31 Pages; ManufacturerAMS; Websitehttps://ams.com/zh

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AMS73CAG02808RAUJH7E Overview

HIGH PERFORMANCE 1Gbit DDR3 SDRAM

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AMS73CAG01808RA

HIGH PERFORMANCE 1Gbit DDR3 SDRAM

8 BANKS X 16Mbit X 8

- H7

DDR3-1066

Clock Cycle Time ( t

CK6, CWL=5

)

Clock Cycle Time ( t

CK7, CWL=6

)

Clock Cycle Time ( t

CK8, CWL=6

)

Clock Cycle Time ( t

CK9, CWL=7

)

Clock Cycle Time ( t

CK10, CWL=7

)

System Frequency (f

CK max

)

2.5 ns

1.875 ns

533 MHz

- I9

DDR3-1333

2.5 ns

1.875 ns

1.5 ns

667 MHz

Specifications

Features

Density : 1G bits

Organization : 16M words x 8 bits x 8 banks

Package :

- 78-ball FBGA

- Lead-free (RoHS compliant) and Halogen-free

Power supply : VDD, VDDQ = 1.5V ± 0.075V

Data rate : 1333Mbps/1066Mbps (max.)

1KB page size

- Row address: A0 to A13

- Column address: A0 to A9

Eight internal banks for concurrent operation

Interface : SSTL_15

Burst lengths (BL) : 8 and 4 with Burst Chop (BC)

Burst type (BT) :

- Sequential (8, 4 with BC)

- Interleave (8, 4 with BC)

CAS Latency (CL) : 5, 6, 7, 8, 9, 10, 11

CAS Write Latency (CWL) : 5, 6, 7, 8

Precharge : auto precharge option for each burst ac-

cess

Driver strength : RZQ/7, RZQ/6 (RZQ = 240

Ω)

Refresh : auto-refresh, self-refresh

Refresh cycles :

- Average refresh period

7.8

μs

at 0°C

≤

+85°C

3.9

μs

at +85°C < Tc

≤

+95°C

Operating case temperature range

- Tc = 0°C to +95°C

Double-data-rate architecture; two data transfers per

clock cycle

The high-speed data transfer is realized by the 8 bits

prefetch pipelined architecture

Bi-directional differential data strobe (DQS and DQS)

is transmitted/received with data for capturing data at

the receiver

DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

Differential clock inputs (CK and CK)

DLL aligns DQ and DQS transitions with CK transitions

Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

Data mask (DM) for write data

Posted CAS by programmable additive latency for bet-

ter command and data bus efficiency

On-Die Termination (ODT) for better signal quality

- Synchronous ODT

- Dynamic ODT

- Asynchronous ODT

Multi Purpose Register (MPR) for pre-defined pattern

read out

ZQ calibration for DQ drive and ODT

Programmable Partial Array Self-Refresh (PASR)

RESET pin for Power-up sequence and reset function

SRT range : Normal/extended

Programmable Output driver impedance control

Device Usage Chart

Operating

Temperature

Range

0°C

≤

95°C

-40°C

≤

95°C

AMS73CAG01808RA

Rev.1.0 December 2010

Package Outline

78-ball FBGA

•

- H7

•

Speed

- I9

•

Std.

•

Power

•

Temperature

Mark

Blank

AMS73CAG01808RA

Signal Pin Description

CK, CK

Type

Input

Function

Clock:

CK and CK are differential clock inputs. All address and control input signals are sampled on

the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to

the crossings of CK and CK

Clock Enable:

CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input

buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh oper-

ation (all banks idle), or Active Power-Down (Row Active in any bank). CKE is asynchronous for self

refresh exit. After V

REFCA

has become stable during the power on and initialization sequence, it must

be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout

read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-

down. Input buffers, excluding CKE, are disabled during Self -Refresh.

Chip Select:

All commands are masked when CS is registered HIGH. CS provides for external Rank

selection on systems with multiple Ranks. CS is considered part of the command code.

On Die Termination:

ODT (registered HIGH) enables termination resistance internal to the DDR3

SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/TDQS.

The ODT pin will be ignored if the Mode Register (MR1) is pro-grammed to disable ODT.

Command Inputs:

RAS, CAS and WE (along with CS) define the command being entered.

Input Data Mask:

DM is an input mask signal for write data. Input data is masked when DM is sampled

HIGH coinci-dent with that input data during a Write access. DM is sampled on both edges of DQS.

Bank Address Inputs:

BA0 - BA2 define to which bank an Active, Read, Write or Precharge command

is being applied. Bank address also determines which mode register is to be accessed during a MRS

cycle.

Address Inputs:

Provided the row address for Active commands and the column address for Read/

Write commands to select one location out of the memory array in the respective bank. (A10/AP and

A12/BC have additional functions, see below)The address inputs also provide the op-code during

Mode Register Set commands.

Autoprecharge:

A10 is sampled during Read/Write commands to determine whether Autoprecharge

should be per-formed to the accessed bank after the Read/Write operation. (HIGH:Autoprecharge;

LOW: No Autoprecharge)A10 is sampled during a Precharge command to determine whether the Pre-

charge applies to one bank (A10 LOW) or all banks (A10 HIGH). if only one bank is to be precharged,

the bank is selected by bank addresses.

Burst Chop:

A12 is sampled during Read and Write commands to determine if burst chop(on-the-fly)

will be per-formed. (HIGH : no burst chop, LOW : burst chopped). See command truth table for details.

Active Low Asynchronous Reset:

Reset is active when RESET is LOW, and inactive when RESET

is HIGH. RESET must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC

high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V for DC low.

Data Input/ Output:

Bi-directional data bus.

Data Strobe:

Output with read data, input with write data. Edge-aligned with read data, centered in

write data. The data strobe DQS is paired with differential signal DQS to provide differential pair sig-

naling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only and

does not support single-ended.

CKE

Input

ODT

Input

RAS, CAS, WE

BA0 - BA2

Input

A0 - A13

Input

A10 / AP

Input

A12 / BC

RESET

Input

DQ0 - DQ7

DQS, DQS

Input/

Output

Input/

Output

AMS73CAG01808RA

Rev. 1.0 December 2010

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