5962R1020203QXC datasheet, PDF

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5962R1020203QXC: DescriptionSRAM,; Categorystorage storage; File Size535KB，31 Pages; ManufacturerAeroflex; Websitehttp://www.aeroflex.com/

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5962R1020203QXC Overview

SRAM,

5962R1020203QXC Parametric

Parameter Name	Attribute value
Maker	Aeroflex
package instruction	,
Reach Compliance Code	unknown
total dose	100k Rad(Si) V

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REVISIONS

LTR

DESCRIPTION

Vendor requested correction to Table IA; parameter (Write disable

time - t

WHWL

) from 1 ns to 2 ns minimum. ksr

Vendor requested corrections to Table IA; footnote additions and

deletions for I

DD1

, I

DD2

, t

EFQZ

, t

ETMX

. Added lid and lead details to

Figure 1. Figure 4, delete footnote. Figure 6, corrected title of EDAC

programming configuration table. Updated boilerplate. glg

Vendor requested corrections to Table IA; t

AVCL

, and additions of

CHAV

, t

CLAX

. Corrections to sections 1.3, 1.5 and Table IB.

Corrections to Figure 5, EDAC Control register cycle waveforms.

Removed class M references to meet current boilerplate

requirements. glg

DATE (YR-MO-DA)

10-07-07

11-10-19

APPROVED

Charles F. Saffle

13-04-03

Charles F. Saffle

REV

SHEET

REV

SHEET

REV STATUS

OF SHEETS

PMIC N/A

REV

SHEET

PREPARED BY

Kenneth Rice

CHECKED BY

Rajesh Pithadia

APPROVED BY

Charles F. Saffle

DRAWING APPROVAL DATE

10-06-15

STANDARD

MICROCIRCUIT

DRAWING

THIS DRAWING IS

AVAILABLE FOR USE BY All

DEPARTMENTS AND

AGENCIES OF THE

DEPARTMENT OF DEFENSE

DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990

http://www.landandmaritime.dla.mil

MICROCIRCUIT, MEMORY, DIGITAL,

CMOS, 1MEG X 32-BIT (32M),

RADIATION-HARDENED, DUAL

VOLTAGE SRAM with embedded EDAC,

MULTICHIP MODULE

SIZE

SHEET

1 OF

5962-E335-13

AMSC N/A

REVISION LEVEL

CAGE CODE

67268

5962-10202

DSCC FORM 2233

APR 97

2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.

Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation.

AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM)

ASTM Standard F1192

Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by

Heavy Ion Irradiation of Semiconductor Devices.

(Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor Drive,

West Conshohocken, PA 19428-2959;

http://www.astm.org.)

JEDEC INTERNATIONAL (JEDEC)

JESD 78

IC Latch-Up Test.

(Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA

22201;

http://www.jedec.org.)

(Non-Government standards and other publications are normally available from the organizations that prepare or distribute the

documents. These documents also may be available in or through libraries or other informational services.)

2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of

this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific

exemption has been obtained.

3. REQUIREMENTS

3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535

and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM

plan shall not affect the form, fit, or function as described herein.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in

MIL-PRF-38535 and herein for device classes Q and V.

3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.

3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 3.

3.2.4 Output load circuit. The output load circuit shall be as specified on figure 4.

3.2.5 Timing waveforms. The timing waveforms shall be as specified on figure 5.

3.2.6 EDAC configuration. EDAC configuration tables and definitions are specified on figure 6.

3.2.7 Radiation test circuit. The radiation test circuit shall be maintained under document revision level control by the

manufacturer and shall be made available to the preparing or acquiring activity upon request.

3.2.8 Functional tests. Various functional tests used to test this device are contained in appendix A (herein). If the test patterns

cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be allowed.

For device classes Q and V, alternate test patterns shall be under the control of the device manufacturer’s Technology Review

Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity upon request.

3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical

performance characteristics and postirradiation parameter limits are as specified in Table IA and shall apply over the full case

operating temperature range.

STANDARD

MICROCIRCUIT DRAWING

DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-10202

SHEET

5962R1020203QXC Related Products

	5962R1020203QXC	5962R1020201VXC	5962R1020204QXC	5962R1020201QXC
Description	SRAM,	SRAM,	Standard SRAM, 1MX32, 20ns, CMOS, CQFP132,	SRAM,
Maker	Aeroflex	Aeroflex	Aeroflex	Aeroflex
Reach Compliance Code	unknown	unknown	unknown	unknown
total dose	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V

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