LT4936 datasheet, PDF - EEWORLD Datasheet

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LT4936: DescriptionPower Field-Effect Transistor, 5.1A I(D), 30V, 0.036ohm, 2-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, SOP-8; CategoryDiscrete semiconductor The transistor; File Size766KB，6 Pages; ManufacturerLITEON; Websitehttp://optoelectronics.liteon.com/en-global/Home/index; Lite-On began producing LED lamps in 1975; the company has steadily grown to become one of the world's largest manufacturers of optoelectronics products by providing customers with visible and infrared product solutions. High-volume production of commercial and application-specific products, as well as strong R&D and vertical integration capabilities have proven to be key and differentiating factors in Lite-On's success.

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LT4936 Overview

Power Field-Effect Transistor, 5.1A I(D), 30V, 0.036ohm, 2-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, SOP-8

LT4936 Parametric

Parameter Name	Attribute value
Maker	LITEON
Parts packaging code	SOT
package instruction	SMALL OUTLINE, R-PDSO-G8
Contacts	8
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	ULTRA-LOW RESISTANCE
Configuration	SEPARATE, 2 ELEMENTS WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage	30 V
Maximum drain current (ID)	5.1 A
Maximum drain-source on-resistance	0.036 Ω
FET technology	METAL-OXIDE SEMICONDUCTOR
JESD-30 code	R-PDSO-G8
Number of components	2
Number of terminals	8
Operating mode	ENHANCEMENT MODE
Maximum operating temperature	150 °C
Package body material	PLASTIC/EPOXY
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Polarity/channel type	N-CHANNEL
Maximum pulsed drain current (IDM)	30 A
Certification status	Not Qualified
surface mount	YES
Terminal form	GULL WING
Terminal location	DUAL
transistor applications	SWITCHING
Transistor component materials	SILICON

LT4936 Preview

LT4936

Dual N-Channel 30-V Power MOSFET

GENERAL DESCRIPTION

The LT4936 is the Dual N-Channel logic enhancement

mode power field effect transistors are produced using

high cell density, DMOS trench technology. This high

density process is especially tailored to minimize on-state

resistance. These devices are particularly suited for low

voltage application such as cellular phone and notebook

computer power management and other battery powered

circuits where high-side switching, and low in-line power

loss are needed in a very small outline surface mount

package.

FEATURES

●

RDS(ON)

≦

36m @VGS=10V

●

RDS(ON)

≦

45m @VGS=4.5V

●

Super high density cell design for extremely low R

DS(ON)

●

Exceptional on-resistance and maximum DC current

capability

APPLICATIONS

●

Power Management

●

DC/DC Converter

●

LCD TV & Monitor Display inverter

●

CCFL inverter

CONFIGURATION

(SOP-8)

Top View

Absolute Maximum Ratings

=25℃ Unless Otherwise Noted)

Parameter

Drain-Source Voltage

Gate-Source Voltage

Continuous Drain

Current(TJ=150℃)

Pulsed Drain Current

Continuous Source Current (Diode Conduction)

=25℃

Maximum Power Dissipation

Operating Junction Temperature

Storage Temperature Range

Thermal Resistance-Junction to Ambient

Thermal Resistance-Junction to Case

The *

Symbol

DSS

GSS

=25℃

=70℃

stg

θJA

θJC

10 secs

Steady State

±20

Unit

6.6

5.1

1.7

2.5

1.5

-55 to 150

5.1

0.9

1.5

0.9

℃

=70℃

℃/W

The device mounted on 1in

FR4 board with 2 oz copper

Rev 1. Oct. 2010

Mar,2007-Ver4.0

LT4936

Dual N-Channel 30-V Power MOSFET

Electrical Characteristics

=25℃ Unless Otherwise Specified)

Symbol

STATIC

DSS

GS(th)

GSS

Drain-Source Breakdown Voltage

Gate Threshold Voltage

Gate Leakage Current

=0V, I

=250μA

, I

=250μA

=0V, V

=±20V

=30V, V

=0V

DSS

Zero Gate Voltage Drain Current

Parameter

Conditions

Min

1.0

Typ

Max

Unit

1.4

3.0

±100

=30V, V

=0V

=55℃

μA

0.8

1.2

mΩ

D(ON)

DS(ON)

DYNAMIC

Ciss

Coss

Crss

Qgs

Qgd

On-State Drain Current

≧

5V, V

=10V

=10V, I

= 5.9A

=4.5V, I

= 4.9A

=1.7A, V

=0V

Drain-Source On-Resistance

Diode Forward Voltage

Gate resistance

Input capacitance

Output Capacitance

Reverse Transfer Capacitance

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

Turn-On Delay Time

Turn-On Rise Time

Turn-Off Delay Time

Turn-Off Fall time

=0V, V

=0V, f=1MHz

0.8

380

450

=15V, V

=0V, f=1.0MHz

=15V, V

=10V, I

=5.9A

3.5

d(on)

d(off)

=15V, R

=15Ω

=1.0A, V

GEN

=10V

=6Ω

Notes: a. Pulse test; pulse width

≦

300us, duty cycle≦ 2%

Rev 1. Oct. 2010

Mar,2007-Ver4.0

LT4936

Dual N-Channel 30-V Power MOSFET

Typical Characteristics (T

=25℃ Noted)

℃

Rev 1. Oct. 2010

Mar,2007-Ver4.0

LT4936

Dual N-Channel 30-V Power MOSFET

Typical Characteristics (T

=25℃ Noted)

℃

Rev 1. Oct. 2010

Mar,2007-Ver4.0

LT4936

Dual N-Channel 30-V Power MOSFET

SOP-8 Package Outline

DIM

MILLIMETERS

MIN

1.35

0.10

0.35

0.18

4.80

3.80

1.27 BSC

5.80

0.25

0.40

0°

6.20

0.50

1.25

7°

MAX

1.75

0.25

0.49

0.25

5.00

4.00

Rev 1. Oct. 2010

Mar,2007-Ver4.0

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