DM74S280M datasheet, PDF - EEWORLD Datasheet

EEWORLDEEWORLD

Datasheet

Datasheet> All Categories > logic> logic> DM74S280M

DM74S280M: DescriptionS SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, PDSO14, 0.150 INCH, PLASTIC, SOIC-14; Categorylogic logic; File Size104KB，4 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/

Stay tuned Parametric Compare

DM74S280M Overview

S SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, PDSO14, 0.150 INCH, PLASTIC, SOIC-14

DM74S280M Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Texas Instruments
Parts packaging code	SOIC
package instruction	SOP, SOP14,.25
Contacts	14
Reach Compliance Code	unknown
Other features	ODD/EVEN PARITY GENERATOR
series	S
JESD-30 code	R-PDSO-G14
JESD-609 code	e0
length	8.65 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	PARITY GENERATOR/CHECKER
Number of digits	9
Number of functions	1
Number of terminals	14
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP14,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
power supply	5 V
Maximum supply current (ICC)	105 mA
propagation delay (tpd)	21 ns
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	TTL
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	3.9 mm

DM74S280M Related Products

	DM74S280M	DM74S280N	DM54S280J/883	DM54S280W/883	DM54S280J/883B	DM74S280MX
Description	S SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, PDSO14, 0.150 INCH, PLASTIC, SOIC-14	S SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, PDIP14, PLASTIC, DIP-14	IC S SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, CDIP14, CERAMIC, DIP-14, Arithmetic Circuit	S SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, CDFP14, CERAMIC, FP-14	S SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, CDIP14, DIP-14	S SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, PDSO14, 0.150 INCH, PLASTIC, SOIC-14
Parts packaging code	SOIC	DIP	DIP	DFP	DIP	SOIC
package instruction	SOP, SOP14,.25	DIP, DIP14,.3	DIP, DIP14,.3	DFP, FL14,.3	DIP, DIP14,.3	SOP,
Contacts	14	14	14	14	14	14
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown
series	S	S	S	S	S	S
JESD-30 code	R-PDSO-G14	R-PDIP-T14	R-GDIP-T14	R-GDFP-F14	R-GDIP-T14	R-PDSO-G14
Logic integrated circuit type	PARITY GENERATOR/CHECKER	PARITY GENERATOR/CHECKER	PARITY GENERATOR/CHECKER	PARITY GENERATOR/CHECKER	PARITY GENERATOR/CHECKER	PARITY GENERATOR/CHECKER
Number of digits	9	9	9	9	9	9
Number of functions	1	1	1	1	1	1
Number of terminals	14	14	14	14	14	14
Maximum operating temperature	70 °C	70 °C	125 °C	125 °C	125 °C	70 °C
Output polarity	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	PLASTIC/EPOXY
encapsulated code	SOP	DIP	DIP	DFP	DIP	SOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	IN-LINE	IN-LINE	FLATPACK	IN-LINE	SMALL OUTLINE
propagation delay (tpd)	21 ns	21 ns	21 ns	21 ns	21 ns	21 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum supply voltage (Vsup)	5.25 V	5.25 V	5.5 V	5.5 V	5.5 V	5.25 V
Minimum supply voltage (Vsup)	4.75 V	4.75 V	4.5 V	4.5 V	4.5 V	4.75 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	NO	NO	YES	NO	YES
technology	TTL	TTL	TTL	TTL	TTL	TTL
Temperature level	COMMERCIAL	COMMERCIAL	MILITARY	MILITARY	MILITARY	COMMERCIAL
Terminal form	GULL WING	THROUGH-HOLE	THROUGH-HOLE	FLAT	THROUGH-HOLE	GULL WING
Terminal pitch	1.27 mm	2.54 mm	2.54 mm	1.27 mm	2.54 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	-
Maker	Texas Instruments	Texas Instruments	-	-	Texas Instruments	Texas Instruments
Other features	ODD/EVEN PARITY GENERATOR	ODD/EVEN PARITY GENERATOR	ODD/EVEN PARITY GENERATOR	ODD/EVEN PARITY GENERATOR	-	ODD/EVEN PARITY GENERATOR
JESD-609 code	e0	e0	e0	e0	e0	-
length	8.65 mm	19.18 mm	19.43 mm	9.5885 mm	-	8.65 mm
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF	-	50 pF
Encapsulate equivalent code	SOP14,.25	DIP14,.3	DIP14,.3	FL14,.3	DIP14,.3	-
power supply	5 V	5 V	5 V	5 V	5 V	-
Maximum supply current (ICC)	105 mA	105 mA	105 mA	105 mA	-	105 mA
Maximum seat height	1.75 mm	5.08 mm	5.08 mm	2.032 mm	-	1.75 mm
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-
width	3.9 mm	7.62 mm	7.62 mm	6.35 mm	-	3.9 mm

Recommended Resources

Dimmable desk lamp circuit

Single-channel infrared receiver with high interference immunity

TDA1180P power amplifier circuit

555 flowerpot water shortage informer circuit

555 simple automatic exposure circuit

Frequent commutation circuit of capacitor-started single-phase motor

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components