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DM74LS138CW

Description
Decoder/Driver, LS Series, Inverted Output, TTL, WAFER
Categorylogic    logic   
File Size102KB,10 Pages
ManufacturerRochester Electronics
Websitehttps://www.rocelec.com/
Download Datasheet Parametric Compare View All

DM74LS138CW Overview

Decoder/Driver, LS Series, Inverted Output, TTL, WAFER

DM74LS138CW Parametric

Parameter NameAttribute value
MakerRochester Electronics
package instructionDIE,
Reach Compliance Codeunknown
ECCN codeEAR99
seriesLS
Input adjustmentSTANDARD
JESD-30 codeX-XUUC-N
Logic integrated circuit typeOTHER DECODER/DRIVER
Number of functions1
Maximum operating temperature70 °C
Minimum operating temperature
Output polarityINVERTED
Package body materialUNSPECIFIED
encapsulated codeDIE
Package shapeUNSPECIFIED
Package formUNCASED CHIP
propagation delay (tpd)40 ns
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyTTL
Temperature levelCOMMERCIAL
Terminal formNO LEAD
Terminal locationUPPER
DM74LS138 • DM74LS139 Decoder/Demultiplexer
August 1986
Revised March 2000
DM74LS138 • DM74LS139
Decoder/Demultiplexer
General Description
These Schottky-clamped circuits are designed to be used
in high-performance memory-decoding or data-routing
applications, requiring very short propagation delay times.
In high-performance memory systems these decoders can
be used to minimize the effects of system decoding. When
used with high-speed memories, the delay times of these
decoders are usually less than the typical access time of
the memory. This means that the effective system delay
introduced by the decoder is negligible.
The DM74LS138 decodes one-of-eight lines, based upon
the conditions at the three binary select inputs and the
three enable inputs. Two active-low and one active-high
enable inputs reduce the need for external gates or invert-
ers when expanding. A 24-line decoder can be imple-
mented with no external inverters, and a 32-line decoder
requires only one inverter. An enable input can be used as
a data input for demultiplexing applications.
The DM74LS139 comprises two separate two-line-to-four-
line decoders in a single package. The active-low enable
input can be used as a data line in demultiplexing applica-
tions.
All of these decoders/demultiplexers feature fully buffered
inputs, presenting only one normalized load to its driving
circuit. All inputs are clamped with high-performance
Schottky diodes to suppress line-ringing and simplify sys-
tem design.
Features
s
Designed specifically for high speed:
Memory decoders
Data transmission systems
s
DM74LS138 3-to-8-line decoders incorporates 3 enable
inputs to simplify cascading and/or data reception
s
DM74LS139 contains two fully independent 2-to-4-line
decoders/demultiplexers
s
Schottky clamped for high performance
s
Typical propagation delay (3 levels of logic)
DM74LS138
DM74LS139
DM74LS138
DM74LS139
21 ns
21 ns
32 mW
34 mW
s
Typical power dissipation
Ordering Code:
Order Number
DM74LS138M
DM74LS138SJ
DM74LS138N
DM74LS139M
DM74LS139SJ
DM74LS139N
Package Number
M16A
M16D
N16E
M16A
M16D
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation
DS006391
www.fairchildsemi.com

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DM74LS138CW DM74LS138SJX
Description Decoder/Driver, LS Series, Inverted Output, TTL, WAFER Decoder/Driver, LS Series, Inverted Output, TTL, PDSO16, 5.30 MM, EIAJ TYPE2, SOP-16
Maker Rochester Electronics Rochester Electronics
package instruction DIE, SOP,
Reach Compliance Code unknown unknown
ECCN code EAR99 EAR99
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