notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.
Rev.
E
08/13/2010
1
IS43R83200B, IS46R83200B
IS43R16160B, IS46R16160B
PIN CONFIGURATION
Package Code B: 60-ball TF-BGA (top view)
(8mm x 13mm Body, 0.8mm x 1.0mm Ball Pitch)
Top View
(Balls seen through the package)
UDQS
LDQS
UDM
LDM
CLK
WE
CAS
A12
RAS
CS
PIN DESCRIPTION: for x16
A0-A12
A0-A8
BA0, BA1
DQ0 – DQ15
CLK,
CLK
CKE
CS
CAS
RAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Column Address Strobe
Command
Row Address Strobe Command
WE
LDM, UDM
LDQS, UDQS
VDD
VDDQ
VSS
VSSQ
VREF
NC
Write Enable
Data Write Mask
Data Strobe
Power
Power Supply for I/O Pins
Ground
Ground for I/O Pins
SSTL_2 reference voltage
No Connection
2
Integrated Silicon Solution, Inc.
Rev.
E
08/13/2010
IS43R83200B, IS46R83200B
IS43R16160B, IS46R16160B
PIN CONFIGURATIONS
66 pin TSOP - Type II for x8, x16
x8
V
DD
DQ0
V
DD
Q
NC
DQ1
V
SS
Q
NC
DQ2
V
DD
Q
NC
DQ3
V
SS
Q
NC
NC
V
DDQ
NC
NC
V
DD
NC
NC
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
x16
V
DD
DQ0
V
DD
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
DD
Q
DQ5
DQ6
V
SS
Q
DQ7
NC
V
DDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
x16
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SSQ
UDQS
NC
VREF
VSS
UDM
CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
x8
V
SS
DQ7
V
SS
Q
NC
DQ6
V
DD
Q
NC
DQ5
V
SS
Q
NC
DQ4
V
DD
Q
NC
NC
V
SSQ
DQS
NC
VREF
VSS
DM
CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
PIN DESCRIPTION:
A0-A12
A0-A8 (x16)
A0-A9 (x8)
BA0, BA1
DQ0 – DQ15 (x16)
DQ0 – DQ7 (x8)
CLK,
CLK
CKE
CS
CAS
RAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Column Address Strobe
Command
Row Address Strobe
Command
WE
LDM, UDM (x16)
DM (x8)
LDQS, UDQS (x16)
DQS (x8)
VDD
VDDQ
VSS
VSSQ
VREF
NC
Write Enable
Data Write Mask
Data Strobe
Power
Power Supply for I/O Pins
Ground
Ground for I/O Pins
SSTL_2 reference voltage
No Connection
Integrated Silicon Solution, Inc.
Rev.
E
08/13/2010
3
IS43R83200B, IS46R83200B
I
Preliminary
IS43R16160B, IS46R16160B
I
PIN FUNCTION
SYMBOL
TYPE
DESCRIPTION
Zentel Electronics Corporation
A3S56D30/40ETP
256M Double Data Rate Synchronous DRAM
CLK, /CLK
Input
Clock: CLK and /CLK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CLK and
negative edge of /CLK. Output (read) data is referenced to the crossings of
CLK and /CLK (both directions of crossing).
Clock Enable: CKE controls internal clock. When CKE is low, internal clock
for the following cycle is ceased. CKE is also used to select auto / self refresh.
After self refresh mode is started, CKE becomes asynchronous input. Self refresh
is maintained as long as CKE is low.
Chip Select: When /CS is high, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
A0-12 specify the Row / Column Address in conjunction with BA0,1. The
Row Address is specified by A0-12. The Column Address is specified by
A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge
option. When A10 is high at a read / write command, an auto precharge is
performed. When A10 is high at a precharge command, all banks are
precharged.
Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
Data Input/Output: Data bus
Data Strobe: Output with read data, input with write data. Edge-aligned
with read data, centered in write data. Used to capture write data.
For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS
correspond to the data on DQ8-DQ15
Input Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ
and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7;
UDM corresponds to the data on DQ8-DQ15.
Power Supply for the memory array and peripheral circuitry.
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