1-to-21, Differential HCSL Fanout
Buffer
ICS851021
DATA SHEET
General Description
The ICS851021 is a 1-to-21 Differential HCSL Fanout Buffer. The
ICS851021 is designed to translate any differential signal levels to
differential HCSL output levels. An external reference resistor is
used to set the value of the current supplied to an external
load/termination resistor. The load resistor value is chosen to equal
the value of the characteristic line impedance of 50Ω. The
ICS851021 is characterized at an operating supply voltage of 3.3V.
The differential HCSL outputs, accurate crossover voltage and duty
cycle make the ICS851021 ideal for interfacing to PCI Express and
FBDIMM applications.
Features
•
•
•
•
•
•
•
•
•
•
Twenty-one differential HCSL outputs
Translates any differential input signal (LVPECL, LVHSTL, LVDS,
HCSL) to HCSL levels without external bias networks
Maximum output frequency: 250MHz
Output skew: 395ps (maximum)
Part-to-part skew: 335ps (maximum)
Output drift: 140ps (maximum)
V
OH
: 850mV (maximum)
Full 3.3V supply voltage
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
0°C to 70°C ambient operating temperature
Block Diagram
CLK
nCLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
Q9
nQ9
Q10
nQ10
IREF
Q20
nQ20
Q19
nQ19
Q18
nQ18
Q17
nQ17
Q16
nQ16
Q15
nQ15
Q14
nQ14
Q13
nQ13
Q12
nQ12
Q11
nQ11
Pin Assignment
Q20
nQ19
Q19
V
DD
nCLK
CLK
Q0
V
DD
nQ20
GND
nQ2
Q2
V
DD
nQ1
Q1
nQ0
Q3
nQ3
V
DD
Q4
nQ4
GND
Q5
nQ5
V
DD
Q6
nQ6
Q7
nQ7
V
DD
Q8
nQ8
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
1
2
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
nQ9
V
DD
Q10
nQ10
V
DD
V
DD
GND
RREF
Q9
nc
Q11
nQ11
V
DD
Q12
nQ12
GND
nQ18
Q18
V
DD
nQ17
Q17
GND
nQ16
Q16
V
DD
nQ15
Q15
nQ14
Q14
V
DD
nQ13
Q13
ICS851021
64-Lead TQFP, E-Pad
10mm x 10mm x 1.0mm package body
Y Package
Top View
ICS851021AY REVISION B
AUGUST 24, 2010
1
©2010 Integrated Device Technology, Inc.
ICS851021 Data Sheet
1-to-21, DIFFERENTIAL HCSL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 2
3, 9, 14, 21, 24, 25, 29,
35, 40, 46, 52, 57, 62
4, 5
6, 17, 32, 43, 49
7, 8
10, 11
12, 13
15, 16
18
19, 20
22, 23
26
27, 28
30, 31
33, 34
36, 37
38. 39
41, 42
44, 45
47, 48
50
51
53, 54
55, 56
58, 59
60, 61
63, 64
Name
Q3, nQ3
V
DD
Q4, nQ4
GND
Q5, nQ5
Q6, nQ6
Q7, nQ7
Q8, nQ8
RREF
Q9, nQ9
Q10, nQ10
nc
Q11, nQ11
Q12, nQ12
Q13, nQ13
Q14, nQ14
Q15, nQ15
Q16, nQ16
Q17, nQ17
Q18, nQ18
CLK
nCLK
Q19, nQ19
Q20, nQ20
Q0, nQ0
Q1, nQ1
Q2, nQ2
Type
Output
Power
Output
Power
Output
Output
Output
Output
Input
Output
Output
unused
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Output
Output
Output
Output
Output
Description
Differential output pair. Differential HCSL interface levels.
Positive supply pins.
Differential output pair. Differential HCSL interface levels.
Power supply ground.
Differential output pair. Differential HCSL interface levels.
Differential output pair. Differential HCSL interface levels.
Differential output pair. Differential HCSL interface levels.
Differential output pair. Differential HCSL interface levels.
External fixed precision resistor (950
Ω
) from this pin to ground provides a reference
current used for differential current-mode Qx, nQx clock outputs.
Differential output pair. Differential HCSL interface levels.
Differential output pair. Differential HCSL interface levels.
No connect.
Differential output pair. Differential HCSL interface levels.
Differential output pair. Differential HCSL interface levels.
Differential output pair. Differential HCSL interface levels.
Differential output pair. Differential HCSL interface levels.
Differential output pair. Differential HCSL interface levels.
Differential output pair. Differential HCSL interface levels.
Differential output pair. Differential HCSL interface levels.
Differential output pair. Differential HCSL interface levels.
Non-inverting differential input.
Inverting differential clock input.
Differential output pair. Differential HCSL interface levels.
Differential output pair. Differential HCSL interface levels.
Differential output pair. Differential HCSL interface levels.
Differential output pair. Differential HCSL interface levels.
Differential output pair. Differential HCSL interface levels.
Output Driver Current
The ICS851021 outputs are HCSL differential current dr ive with
the current being set with a resistor from I
REF
to ground. For
a
single load
and a 50Ω pc board trace, the drive current would
typically be set with a R
REF
of 950Ω which products an I
REF
of 1.16mA.
The I
REF
is multiplied by a current mirror to an output drive of
12*1.16mA or 13.90mA. See
Figure 1
for current mirror and output
drive details.
I
REF
R
REF
950Ω
R
L
R
L
Figure 1. HCSL Current Mirror and Output Drive
ICS851021AY REVISION B
AUGUST 24, 2010
2
©2010 Integrated Device Technology, Inc.
ICS851021 Data Sheet
1-to-21, DIFFERENTIAL HCSL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
31.8°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 2A. Power Supply DC Characteristics, V
DD
= 3.3V±5%, T
A
= 0°C to 70°C
Symbol
V
DD
I
DD
Parameter
Core Supply Voltage
Power Supply Current; NOTE 1
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
105
Units
V
mA
Table 2B. Differential DC Characteristics, V
DD
= 3.3V±5%, T
A
= 0°C to 70°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input
High Current
Input
Low Current
CLK, nCLK
CLK, nCLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
0.15
GND + 0.5
Minimum
Typical
Maximum
5
5
1.3
V
DD
– 0.85
Units
µA
µA
V
V
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
ICS851021AY REVISION B
AUGUST 24, 2010
3
©2010 Integrated Device Technology, Inc.
ICS851021 Data Sheet
1-to-21, DIFFERENTIAL HCSL FANOUT BUFFER
AC Electrical Characteristics
Table 3. HCSL AC Characteristics, V
DD
= 3.3V±5%, T
A
= 0°C to 70°C
Symbol
f
MAX
t
PD
tsk(o)
tsk(pp)
tjit
tsk(drift)
V
MAX
V
MIN
V
CROSS
∆V
CROSS
Parameter
Output Frequency
Propagation Delay, NOTE 1
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS; refer
to Additive Phase Jitter Section
Output Drift; NOTE 5
Absolute Max Output Voltage; NOTE 6
Absolute Min Output Voltage; NOTE 6
Absolute Crossing Voltage;
NOTE 7, 8, 9
Total Variation of V
CROSS
over all
edges; NOTE 7, 8, 10
Rise/Fall Edge Rate; NOTE 11, 12
Rise/Fall Time Matching; NOTE 13
odc
Output Duty Cycle; NOTE 14
47
0.6
ƒ
≤
150MHz
ƒ
≤
150MHz
500
-150
250
CLK = 200MHz, Integration
Range: 12kHz – 30MHz
0.20
140
850
150
550
140
4.0
20
53
Measured on at V
OX
Measured on at V
OX
1.5
Test Conditions
Minimum
Typical
Maximum
250
2.75
395
335
Units
MHz
ns
ps
ps
ps
ps
mV
mV
mV
mV
V/ns
%
%
NOTE:
Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE:
Current adjust set for V
OH
= 0.7V. Measurements refer to PCIEX outputs only.
NOTE:
Characterized using an R
REF
value of 950
Ω
resistor.
NOTE 1:
Measured from the differential input cross point to the differential output crossing point.
NOTE 2:
Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential output
cross point.
NOTE 3:
This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4:
Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross point.
NOTE 5:
Output Drift is measured as the change in the time placement of the differential cross point for each output on a given device due to
a change in temperature and supply voltage. Measured at the differential cross point.
NOTE 6:
Measurement using R
REF
= 950Ω, R
LOAD
= 50Ω..
NOTE 7:
Measurement taken from single-ended waveform.
NOTE 8:
Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.
See Parameter Measurement Information Section.
NOTE 9:
Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement. See Parameter Measurement Information Section.
NOTE 10:
Defined as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the
V
CROSS
for any particular system. See Parameter Measurement Information Section.
NOTE 11:
Measurement taken from differential waveform.
NOTE 12:
Measurement from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic
through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
NOTE 13:
Matching applies to rising edge rate for Qx and falling edge rate for nQx. It is measured using a ±75mV window centered on the
median cross point where Qx rising meets nQx falling.
NOTE 14:
Assuming 50% input duty cycle. Data taken at ƒ
≤
200MHz, unless otherwise specified.
ICS851021AY REVISION B
AUGUST 24, 2010
4
©2010 Integrated Device Technology, Inc.
ICS851021 Data Sheet
1-to-21, DIFFERENTIAL HCSL FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the
dBc Phase
Noise.
This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 200MHz
12kHz to 30MHz = 0.20ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
ICS851021AY REVISION B
AUGUST 24, 2010
5
©2010 Integrated Device Technology, Inc.
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