Standard SRAM, 128KX16, 55ns, CMOS, PBGA48, 7 X 7 MM, FBGA-48
CY62137VLL-55BAI Parametric
Parameter Name
Attribute value
Is it Rohs certified?
incompatible
Maker
Cypress Semiconductor
Parts packaging code
BGA
package instruction
7 X 7 MM, FBGA-48
Contacts
48
Reach Compliance Code
not_compliant
ECCN code
3A991.B.2.A
Maximum access time
55 ns
I/O type
COMMON
JESD-30 code
S-PBGA-B48
JESD-609 code
e0
length
7 mm
memory density
2097152 bit
Memory IC Type
STANDARD SRAM
memory width
16
Number of functions
1
Number of terminals
48
word count
131072 words
character code
128000
Operating mode
ASYNCHRONOUS
Maximum operating temperature
85 °C
Minimum operating temperature
-40 °C
organize
128KX16
Output characteristics
3-STATE
Package body material
PLASTIC/EPOXY
encapsulated code
TFBGA
Encapsulate equivalent code
BGA48,6X8,30
Package shape
SQUARE
Package form
GRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/Serial
PARALLEL
Peak Reflow Temperature (Celsius)
NOT SPECIFIED
power supply
3 V
Certification status
Not Qualified
Maximum seat height
1.2 mm
Maximum standby current
0.0000075 A
Minimum standby current
1 V
Maximum slew rate
0.015 mA
Maximum supply voltage (Vsup)
3.6 V
Minimum supply voltage (Vsup)
2.7 V
Nominal supply voltage (Vsup)
3 V
surface mount
YES
technology
CMOS
Temperature level
INDUSTRIAL
Terminal surface
Tin/Lead (Sn/Pb)
Terminal form
BALL
Terminal pitch
0.75 mm
Terminal location
BOTTOM
Maximum time at peak reflow temperature
NOT SPECIFIED
width
7 mm
CY62137VLL-55BAI Preview
1*CY62137V18
MoBL2™
CY62137V MoBL™
128K x 16 Static RAM
Features
• Low voltage range:
— CY62137V: 2.7V–3.6V
• Ultra-low active, standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
high-impedance state when: deselected (CE HIGH), outputs
are disabled (OE HIGH), BHE and BLE are disabled (BHE,
BLE HIGH), or during a write operation (CE LOW, and WE
LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
16
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The CY62137V is available in 48-ball FBGA and standard
44-pin TSOP Type II (forward pinout) packaging.
Functional Description
The CY62137V is a high-performance CMOS static RAM or-
ganized as 131,072 words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL™) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that reduces power con-
sumption by 99% when addresses are not toggling. The device
can also be put into standby mode when deselected (CE
HIGH) or when CE is LOW and both BLE and BHE are HIGH.
The input/output pins (I/O
0
through I/O
15
) are placed in a
Logic Block Diagram
Pin Configurations
TSOP II (Forward)
Top View
DATA IN DRIVERS
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
128K x 16
RAM Array
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
CE
BHE
BLE
Power Down
Circuit
MoBL and More Battery Life are trademarks of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
4
A
3
A
2
A
1
A
0
CE
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
V
SS
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
16
A
15
A
14
A
13
A
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
5
A
6
A
7
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
8
A
9
A
10
A
11
NC
ROW DECODER
•
SENSE AMPS
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
February 2, 2001
CY62137V MoBL™
Pin Configurations
(continued)
48-Ball FBGA
1
BLE
I/O
8
I/O
9
V
SS
V
CC
I/O
14
I/O
15
NC
2
OE
BHE
I/O
10
I/O
11
I/O
12
I/O
13
NC
A
8
Top View
4
5
3
A
0
A
3
A
5
NC
NC
A
14
A
12
A
9
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
A
2
CE
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
NC
I/O
0
I/O
2
V
CC
V
SS
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature –65°C to +150°C
Ambient Temperature with
Power Applied−55°C to +125°C
Supply Voltage to Ground Potential–0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[1]
–0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
–0.5V to V
CC
+ 0.5V
Output Current into Outputs (LOW)20 mA
Static Discharge Voltage >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current >200 mA
Operating Range
Device
CY62137V
Industrial
Range
Ambient Temperature
–40°C to +85°C
V
CC
2.7V to 3.6V
Product Portfolio
Power Dissipation (Industrial)
V
CC
Range
Product
CY62137V
V
CC(min.)
2.7V
V
CC(typ.)
2]
3.0V
V
CC
(max.)
3.6V
Power
LL
Operating (I
CC
)
Typ.
[2]
7 mA
Max.
15 mA
Typ.
[2]
1
µA
Standby (I
SB2
)
Max.
15
µA
Notes:
1. V
IL
(min.) = –2.0V for pulse durations less than 20 ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC
Typ., T
A
= 25°C.
2
CY62137V MoBL™
Electrical Characteristics
Over the Operating Range
CY62137V
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
V
CC
Operating Supply
Current
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
,
CMOS Levels
I
OUT
= 0 mA, f = 1 MHz,
CMOS Levels
I
SB1
Automatic CE
Power-Down Current—
CMOS Inputs
Automatic CE
Power-Down Current—
CMOS Inputs
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V or
V
IN
< 0.3V, f = f
MAX
CE > V
CC
– 0.3V
V
IN
> V
CC
– 0.3V
or V
IN
< 0.3V, f = 0
V
CC
= 3.6V
V
CC
= 3.6V
Test Conditions
I
OH
= –1.0 mA
I
OL
= 2.1 mA
V
CC
= 2.7V
V
CC
= 2.7V
V
CC
= 3.6V
V
CC
= 2.7V
2.2
–0.5
–1
–1
+1
+1
7
Min.
2.4
0.4
V
CC
+ 0.5V
0.8
+1
+1
15
Typ.
[2]
Max.
Unit
V
V
V
V
µA
µA
mA
1
2
100
mA
µA
I
SB2
V
CC
=
3.6V
LL
1
15
µA
9
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
Max.
6
8
Unit
pF
pF
Thermal Resistance
Description
Thermal Resistance
(Junction to Ambient)
[3]
Thermal Resistance
(Junction to Case)
[3]
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
Test Conditions
Still Air, soldered on a 4.25 x 1.125 inch, 4-layer
printed circuit board
Symbol
Θ
JA
Θ
JC
BGA
55
16
TSOPII
60
22
Unit
°C/W
°C/W
3
CY62137V MoBL™
AC Test Loads and Waveforms
R1
V
CC
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
V
CC
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2
R1
V
CC
Typ
10%
GND
Rise Time:
1 V/ns
ALL INPUT PULSES
90%
90%
10%
Fall Time:
1 V/ns
(a)
(b)
(c)
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
V
OUTPUT
Parameters
R1
R2
R
TH
V
TH
3.0V
1105
1550
645
1.75V
Unit
Ohms
Ohms
Ohms
Volts
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
Description
V
CC
for Data Retention
Data Retention Current
V
CC
= 1.0V
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V or
V
IN
< 0.3V
No input may exceed
V
CC
+0.3V
LL
Conditions
[4]
Min.
1.0
0.5
Typ.
[2]
Max.
3.6
7.5
Unit
V
µA
t
CDR[3]
t
R
Chip Deselect to Data
Retention Time
Operation Recovery Time
0
70
ns
ns
Data Retention Waveform
DATA RETENTION MODE
V
CC
V
CC
(min.)
t
CDR
V
DR
> 1.0 V
V
CC
(min.)
t
R
CE
Note:
4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input levels of 0 to V
CC
typ., and output loading of the specified
I
OL
/I
OH
and 30 pF load capacitance.
4
CY62137V MoBL™
Switching Characteristics
Over the Operating Range
[4]
55 ns
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE (7)
t
HZBE
WRITE CYCLE
[8, 9]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
t
BW
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[5, 6]
WE HIGH to Low Z
[5]
BHE / BLE LOW to End of Write
5
50
55
45
45
0
0
40
25
0
20
10
60
70
60
60
0
0
50
30
0
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[5]
OE HIGH to High Z
[5, 6]
CE LOW to Low Z
[5]
CE HIGH to High Z
[5, 6]
CE LOW to Power-Up
CE HIGH to Power-Down
BHE / BLE LOW to Data Valid
BHE / BLE LOW to Low Z
BHE / BLE HIGH to High Z
5
25
0
55
55
5
25
10
25
0
70
70
5
25
10
25
10
55
25
5
25
55
55
10
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
70 ns
Max.
Unit
Notes:
5. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
6. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. If both byte enables are toggled together this value is 10 ns.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
Recently I transplanted qt-embedded-3.3.8 on the 2410 development board. The cross-compilation steps are as follows: arm-linux-cross-2.95.3.tar.bz2 has been installed in /usr/local/arm/2.95.3, and the...
:) When it comes to the topic of safety, people will immediately think of natural disasters such as floods, fires, earthquakes, etc., but in fact, safety is an important issue for all walks of life. W...
:)Recently, Intel demonstrated a virtual fitting technology. This machine is a specially made transparent screen + remote control. The machine is placed in a clothing store and projects the store scen...
Abstract: A high-performance Chinese digital speech recognition (MDSR) system is proposed. The MDSR system uses Mel-frequency cepstral coefficients (MFCC) as the main speech feature parameters, and ex...
Embedded System
京公网安备 11010802033920号
EEWORLD
