Memory Module Specifications
KVR13LR9S4L/8
8GB 1Rx4 1G x 72-Bit PC3L-10600
CL9 Registered w/Parity 240-Pin DIMM
DESCRIPTION
This document describes ValueRAM's 1G x 72-bit (8GB)
DDR3L-1333 CL9 SDRAM (Synchronous DRAM), low voltage,
VLP, registered w/parity, 1Rx4 ECC memory module, based on
eighteen 1G x 4-bit FBGA components. The SPD is pro-
grammed to JEDEC standard latency DDR3-1333 timing of
9-9-9 at 1.35V and 1.5V. This 240-pin DIMM uses gold contact
fingers. The electrical and mechanical specifications are as
follows:
UL Rating
Operating Temperature
Storage Temperature
SPECIFICATIONS
CL(IDD)
Row Cycle Time (tRCmin)
Refresh to Active/Refresh
Command Time (tRFCmin)
Row Active Time (tRASmin)
Maximum Operating Power
9 cycles
49.5ns (min.)
260ns (min.)
36ns (min.)
(1.35V) = 4.919 W*
(1.50V) = 5.601 W*
94 V - 0
0
o
C to 85
o
C
-55
o
C to +100
o
C
FEATURES
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JEDEC standard 1.35V (1.28V ~ 1.45V) and 1.5V (1.425V ~
1.575V) Power Supply
VDDQ = 1.35V (1.28V ~ 1.45V) and 1.5V (1.425V ~ 1.575V)
667MHz fCK for 1333Mb/sec/pin
8 independent internal bank
Programmable CAS Latency: 9, 8, 7, 6
Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
Programmable CAS Write Latency(CWL) = 7 (DDR3-1333)
8-bit pre-fetch
Burst Length: 8 (Interleave without any limit, sequential with
starting address “000” only), 4 with tCCD = 4 which does not
allow seamless read or write [either on the fly using A12 or
MRS]
Bi-directional Differential Data Strobe
Internal(self) calibration : Internal self calibration through ZQ
pin (RZQ : 240 ohm ± 1%)
On Die Termination using ODT pin
On-DIMM thermal sensor (Grade B)
Average Refresh Period 7.8us at lower than TCASE 85°C,
3.9us at 85°C < TCASE < 95°C
Asynchronous Reset
PCB : Height 0.740” (18.75mm), double sided component
*Power will vary depending on the SDRAM and
Register/PLL used.
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Continued >>
Document No. VALUERAM1256-001.B00
01/22/13
Page 1
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