TCP-4112UB
1.2 pF Passive Tunable
Integrated Circuits (PTIC)
Introduction
ON Semiconductor’s PTICs have excellent RF performance and
power consumption, making them suitable for any mobile handset or
radio application. The fundamental building block of our PTIC
product line is a tunable material called ParaScant, based on Barium
Strontium Titanate (BST). PTICs have the ability to change their
capacitance from a supplied bias voltage generated by the Control IC.
The 1.2 pF ultra−high tuning PTICs are available as wafer-level chip
scale packages (WLCSP).
Key Features
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WLCSP4
0.626x0.609
CASE 567LN
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•
•
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Ultra−High Tuning Range and Operation up to 24 V
Usable Frequency Range: from 700 MHz to 2.7 GHz
High Quality Factor (Q) for Low Loss
High Power Handling Capability
Compatible with PTIC Control IC TCC-10x, 20x
WLCSP Package: 0.609 x 0.626 x 0.310 mm (4 bump)
These devices are Pb−Free and RoHS Compliant
MARKING DIAGRAM
Typical Applications
FUNCTIONAL BLOCK DIAGRAM
PTIC
RF1
RF2
Multi-band, Multi-standard, Advanced and Simple Mobile Phones
Tunable Antenna Matching Networks
Tunable RF Filters
Active Antennas
Bias
PTIC Functional Block Diagram
ORDERING INFORMATION
Device
TCP−4112UB−DT
Package
WLCSP4
(Pb−Free)
Shipping
†
4000 Units /
7” Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2015
1
July, 2018 − Rev. 1
Publication Order Number:
TCP−4112UB/D
TCP−4112UB
DC Bias 1
A1
A2
NC
RF2
B1
B2
RF1
Figure 1. PTIC Functional Block Diagram
Table 1. SIGNAL DESCRIPTIONS
Ball / Pad Number
A1
B1
A2
B2
Pin Name
DC Bias 1
RF2
NC
RF1
Description
DC Bias Voltage
RF Input / Output
Not Connected
RF Input / Output
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TCP−4112UB
TYPICAL SPECIFICATIONS
Representative Performance Data at 255C
Table 2. PERFORMANCE DATA
Parameter
Operating Bias Voltage
Capacitance (V
bias
= 2 V)
Capacitance (V
bias
= 24 V)
Tuning Range (1 V - 24 V)
Tuning Range (2 V - 24 V)
Leakage Current (WLCSP)
Operating Frequency
Quality Factor @ 700 MHz, 10 V
Quality Factor @ 2.4 GHz, 10 V
IP3 (V
bias
= 2 V)
[1,3]
IP3 (V
bias
= 24 V)
[1,3]
2nd Harmonic (V
bias
= 2 V)
[2,3]
2nd Harmonic (V
bias
= 24 V)
[2,3]
3rd Harmonic (V
bias
= 2 V)
[2,3]
3rd Harmonic (V
bias
= 24 V)
[2,3]
Transition Time (Cmin
³
Cmax)
[4]
Transition Time (Cmax
³
Cmin)
[4]
1.
2.
3.
4.
f
1
= 850 MHz, f
2
= 860 MHz, Pin 25 dBm/Tone
850 MHz, Pin +34 dBm
IP3 and Harmonics are measured in the shunt configuration in a 50
W
environment
RF
IN
and RF
OUT
are both connected to DC ground
700
90
60
70
80
-65
-75
-40
-70
80
70
dBm
dBm
dBm
dBm
dBm
dBm
ms
ms
Min
1.0
1.08
0.230
4.80
4.20
1.20
0.255
5.30
4.70
Typ
Max
24
1.32
0.281
6.00
5.30
0.5
2700
mA
MHz
Units
V
pF
pF
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TCP−4112UB
Representative performance data at 255C for 1.2 pF WLCSP Package
Figure 2. Capacitance
Figure 3. Harmonic Power*
Figure 4. IP3*
*Data shown is representative only.
Figure 5. Q*
Table 3. ABSOLUTE MAXIMUM RATINGS
Parameter
Input Power
Bias Voltage
Operating Temperature Range
Storage Temperature Range
ESD − Human Body Model
Rating
+40
+25 (Note 5)
−30 to +85
−55 to +125
Class 1B JEDEC HBM Standard (Note 6)
Units
dBm
V
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
5. WLCSP: Recommended Bias Voltage not to exceed 24 V.
6. Class 1B defined as passing 500 V, but may fail after exposure to 1000 V ESD pulse.
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TCP−4112UB
ASSEMBLY CONSIDERATIONS AND REFLOW PROFILE
The following assembly considerations should be observed:
Cleanliness
These chips should be handled in a clean environment.
Electro-static Sensitivity
ON Semiconductor’s PTICs are ESD Class 1B sensitive.
The proper ESD handling procedures should be used.
Mounting
The WLCSP PTIC is fabricated for Flip Chip solder
mounting. Connectivity to the RF and Bias terminations on
the PTIC die is established through SAC305 solder balls
with 65
mm
nominal height (45
mm
to 85
mm
height
variation). The PTIC die is RoHS-compliant and compatible
with lead-free soldering profile.
Molding
The PTIC die is compatible for over-molding or
under-fill.
Figure 6. Reflow Profile
ORIENTATION OF THE PTIC FOR OPTIMUM LOSSES
When configuring the PTIC in your specific circuit
design, at least one of the RF terminals must be connected
to DC ground. If minimum transition times are required, DC
ground on both RF terminals is recommended. To minimize
losses, the PTIC should be oriented such that RF2 is at the
lower RF impedance of the two RF nodes. A shunt PTIC, for
example, should have RF2 connected to RF ground.
RF
RF1
(PTIC Pad)
ANT
RF2
(PTIC Pad)
Bias
Figure 7. PTIC Orientation Functional Block
Diagram
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