MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM64Z836/D
Product Proposal
256K x 36 and 512K x 18
Bit Pipelined ZBT™ RAM
Synchronous Fast Static RAM
The ZBT RAM is an 8M–bit synchronous fast static RAM designed to provide
Zero Bus Turnaround™. The ZBT RAM allows 100% use of bus cycles during
back–to–back read/write and write/read cycles. The MCM64Z836 (organized as
256K words by 36 bits) and the MCM64Z918 (organized as 512K words by 18
bits) are fabricated in Motorola’s high performance silicon gate CMOS tech-
nology. This device integrates input registers, an output register, a 2–bit address
counter, and high speed SRAM onto a single monolithic circuit for reduced parts
count in communication applications. Synchronous design allows precise cycle
control with the use of an external positive–edge–triggered clock (CK). CMOS
circuitry reduces the overall power consumption of the integrated functions for
greater reliability.
Addresses (SA), data inputs (DQ), and all control signals except output enable
(G), sleep mode (ZZ), and linear burst order (LBO) are clock (CK) controlled
through positive–edge–triggered noninverting registers.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (CK) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily stored by an edge–
triggered output register and then released to the output buffers at the next rising
edge of clock (CK).
•
2.5 V LVTTL and LVCMOS Compatible
•
MCM64Z836 / 918–225 = 2.6 ns Access / 4.4 ns Cycle (225 MHz)
MCM64Z836 / 918–200 = 3.2 ns Access / 5 ns Cycle (200 MHz)
MCM64Z836 / 918–166 = 3.6 ns Access / 6 ns Cycle (166 MHz)
•
Selectable Burst Sequencing Order (Linear/Interleaved)
•
Internally Self–Timed Write Cycle
•
Sleep Mode (ZZ)
•
Two–Cycle Deselect
•
Byte Write Control
•
ADV Controlled Burst
•
IEEE 1149–1 Sample Only JTAG
•
100–Pin TQFP and 119–Bump PBGA Packages
MCM64Z836
MCM64Z918
TQ PACKAGE
TQFP
CASE 983A–01
ZP PACKAGE
PBGA
CASE 999–02
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by
Micron Technology, Inc. and Motorola, Inc.
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 2
6/2/99
©
Motorola, Inc. 1999
MOTOROLA FAST SRAM
MCM64Z836•MCM64Z918
1
LOGIC BLOCK DIAGRAM
LBO
BURST
ADDRESS
COUNTER
ADDRESS
REGISTER
MEMORY
ARRAY
SA
DATA–IN
REGISTER
CK
CONTROL
LOGIC
CKE
K
K
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
K
DATA–IN
REGISTER
SE1
SE2
SE3
ADV
SW
SBx
G
ZZ
36 OR 18
DQ
CONTROL
REGISTER
CONTROL
LOGIC
K
DATA–OUT
REGISTER
MCM64Z836•MCM64Z918
2
MOTOROLA FAST SRAM
MCM64Z836 PIN ASSIGNMENTS
SA
SA
SE1
SE2
SBd
SBc
SBb
SBa
SE3
VDD
VSS
CK
SW
CKE
G
ADV
NC
SA
SA
SA
1
DQb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
VDD
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQa
A
B
NC
C
D
DQc
E
DQc
F
G
DQc
H
DQc
J
K
DQd
L
DQd
M
VDDQ
N
DQd
P
DQd
R
T
NC
U
NC
SA
TDI
SA
TCK
SA
NC
ZZ
VDDQ TMS
TDO TRST VDDQ
VDD
DQd
SA
VSS
LBO
SA0
VDD
VSS
VDD
DQa
SA
DQa
NC
DQd
VSS
SA1
VSS
DQa
DQa
DQd
VSS
CKE
VSS
DQa VDDQ
DQd
SBd
NC
SBa
DQa
DQa
DQd
VSS
CK
VSS
DQa
DQa
DQc
VSS
NC
SW
VDD
VSS
NC
DQb
DQb
VDDQ VDD
VDD VDDQ
DQc
SBc
SA
SBb
DQb
DQb
VDDQ
DQc
DQc
VSS
VSS
SE1
G
VSS
VSS
DQb
DQb
DQb VDDQ
DQc
VSS
NC
VSS
DQb
DQb
NC
SE2
SA
SA
SA
ADV
VDD
SA
SA
SE3
SA
NC
NC
VDDQ
2
SA
3
SA
4
NC
5
SA
6
SA
7
VDDQ
DQc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
VDD
VDD
VDD
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
LBO
SA
SA
SA
SA
SA1
SA0
NC
NC
VSS
VDD
NC
NC
SA
SA
SA
SA
SA
SA
SA
100–PIN TQFP
TOP VIEW
119–BUMP PGBA
TOP VIEW
Not to Scale
MOTOROLA FAST SRAM
MCM64Z836•MCM64Z918
3
MCM64Z836 TQFP PIN DESCRIPTIONS
Pin Locations
85
89
87
(a) 51, 52, 53, 56, 57, 58, 59, 62, 63
(b) 68, 69, 72, 73, 74, 75, 78, 79, 80
(c) 1, 2, 3, 6, 7, 8, 9, 12, 13
(d) 18, 19, 22, 23, 24, 25, 28, 29, 30
86
31
Symbol
ADV
CK
CKE
DQx
Type
Input
Input
Input
I/O
Description
Synchronous Load/Advance: Loads a new address into counter when
low. RAM uses internally generated burst addresses when high.
Clock: This signal registers the address, data in, and all control signals
except G and LBO.
Clock Enable: Disables the CK input when CKE is high.
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
G
LBO
Input
Input
Asynchronous Output Enable.
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter.
High — interleaved burst counter.
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
Synchronous Burst Address Inputs: The two LSBs of the address field.
These pins must preset the burst address counter values. These inputs
are registered and must meet setup and hold times.
Synchronous Byte Write Inputs: Enables write to byte “x” (byte a, b,
c, d) in conjunction with SW. Has no effect on read cycles.
Synchronous Chip Enable: Active low to enable chip.
Synchronous Chip Enable: Active high for depth expansion.
Synchronous Chip Enable: Active low for depth expansion.
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins.
Sleep Mode: This active high asynchronous signal places the RAM into
the lowest power mode. The ZZ pin disables the RAMs internal clock
when placed in this mode. When ZZ is negated, the RAM remains in
low power mode until it is commanded to READ or WRITE. Data
integrity is maintained upon returning to normal operation.
Core Power Supply.
I/O Power Supply.
Ground.
No Connection: There is no connection to the chip.
32, 33, 34, 35, 44, 45, 46, 47, 48, 49,
50, 81, 82, 83, 99, 100
37, 36
SA
SA0, SA1
Input
Input
93, 94, 95, 96
(a) (b) (c) (d)
98
97
92
88
64
SBx
SE1
SE2
SE3
SW
ZZ
Input
Input
Input
Input
Input
Input
14, 15, 16, 41, 65, 66, 91
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 17, 21, 26, 40, 55, 60, 67,
71, 76, 90
38, 39, 42, 43, 84
VDD
VDDQ
VSS
NC
Supply
Supply
Supply
—
MCM64Z836•MCM64Z918
4
MOTOROLA FAST SRAM
MCM64Z836 PBGA PIN DESCRIPTIONS
Pin Locations
4B
4K
4M
(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P
(b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H
(c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H
(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P
4F
3R
Symbol
ADV
CK
CKE
DQx
Type
Input
Input
Input
I/O
Description
Synchronous Load/Advance: Loads a new address into counter when
low. RAM uses internally generated burst addresses when high.
Clock: This signal registers the address, data in, and all control signals
except G and LBO.
Clock Enable: Disables the CK input when CKE is high.
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
G
LBO
Input
Input
Asynchronous Output Enable.
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter.
High — interleaved burst counter.
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
Synchronous Burst Address Inputs: The two LSBs of the address field.
These pins must preset the burst address counter values. These inputs
are registered and must meet setup and hold times.
Synchronous Byte Write Inputs: Enables write to byte “x” (byte a, b,
c, d) in conjunction with SW. Has no effect on read cycles.
Synchronous Chip Enable: Active low to enable chip.
Synchronous Chip Enable: Active high for depth expansion.
Synchronous Chip Enable: Active low for depth expansion.
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins.
Boundary Scan Pin, Test Clock: If boundary scan is not used, TCK
must be tied to VDD or VSS.
Boundary Scan Pin, Test Data In.
Boundary Scan Pin, Test Data Out.
Boundary Scan Pin, Test Mode Select.
Boundary Scan Pin, Asynchronous Test Reset. If boundary scan is not
used, TRST must be tied to VSS.
Sleep Mode: This active high asynchronous signal places the RAM into
the lowest power mode. The ZZ pin disables the RAMs internal clock
when placed in this mode. When ZZ is negated, the RAM remains in
low power mode until it is commanded to READ or WRITE. Data
integrity is maintained upon returning to normal operation.
Core Power Supply.
I/O Power Supply.
Ground.
No Connection: There is no connection to the chip.
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C,
6C, 4G, 2R, 6R, 3T, 4T, 5T
4N, 4P
SA
SA1, SA0
Input
Input
5L, 5G, 3G, 3L
(a) (b) (c) (d)
4E
2B
6B
4H
4U
3U
5U
2U
6U
7T
SBx
SE1
SE2
SE3
SW
TCK
TDI
TDO
TMS
TRST
ZZ
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
Input
4C, 2J, 4J, 6J, 1R, 4R, 5R
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H, 3K,
5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P
4A, 1B, 7B, 1C, 7C, 4D, 3J, 5J, 7R,
1T, 2T, 6T
VDD
VDDQ
VSS
NC
Supply
Supply
Supply
—
MOTOROLA FAST SRAM
MCM64Z836•MCM64Z918
5
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